CY28159PVCT

CY28159 Clock Generator for Serverworks Grand Champion Chipset Applications 1CY28159 Features • Eight differential CPU clock outputs • One PCI output • One 14.31818 MHz reference clock • Two 48 MHz clocks Table 1. Frequency Selection SEL 100/133 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 S1 0 1 0 1 0 1 0 1 CPU(0:7), CPU#(0:7) 100 MHz 100 MHz 100 MHz Hi-Z 133.3MHz 133.3MHz 200MHz N/A 3V33 33.3MHz 33.3MHz Disable Hi-Z 33.3MHz 33.3MHz 33.3MHz N/A 48M(0,1) 48 MHz Disable Disable Hi-Z 48 MHz Disable 48 MHz N/A Notes Normal Operation Test Mode(recommended) Test Mode (optional) Hi-Z all outputs Optional Optional o7ptional Reserved • All outputs compliant with Intel® specifications • External resistor for current reference • Selection logic for differential swing control, test mode, Hi-Z, power-down and spread spectrum • 48-pin SSOP and TSSOP packages Table 2. Block Diagram Pin Configuration 3V33 VDD 48M0/S0 48M1/S1 VSS VDD CPU0 CPU0# VSS CPU1 CPU1# VDD CPU2 CPU2# VSS CPU3 CPU3# VDD REF SSCG# VSS XIN XOUT VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL100/133 VSS VDDA VSSA PD# VDD CPU4 CPU4# VSS CPU5 CPU5# VDD CPU6 CPU6# VSS CPU7 CPU7# VDD MULT0 MULT1 VSS VSSA IREF VDDA XIN XOUT MultSel(0:1) I_Ref OSC VDDI I Control REF CPU (0:7) CPU (0:7)# SSCG# SEL100/133 VCO 48M(0,1)/S(0,1) PD# S(0,1) VDDL 3V33 VSSL Rev 1.0, November 24, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 CY28159 VSSI Page 1 of 12 www.SpectraLinear.com CY28159 Pin Description Pin 20 Name SSCG I/O[1] PU I O Description When asserted LOW, this pin invokes Spread Spectrum functionality. Spread spectrum is applicable to CPU(0:7), CPU(0:7)#. This pin has a 250-k internal pull-up. Differential host clock outputs. These outputs are used in pairs, (CPU0-0#, CPU1-1#, CPU2-2#, CPU3-3#, CPU4-4#, CPU5-5#, CPU6-6#, and CPU7-7#) for differential clocking of the host bus. CPU(0:7) are 180 degrees out of phase with their complements, CPU(0:7)#. See Table 1 on page 1 This pin establishes the reference current for the internal current steering buffers of the CPU clocks. A resistor is connected from this pin to ground to set the value of this current. Fixed 33.3-MHz clock output. When asserted LOW, this pin invokes a power-down mode by shutting off all the clocks, disabling all internal circuitry, and shutting down the crystal oscillator. The 48M(0:1) and REF clocks are driven LOW during this condition and the CPU clocks are driven HIGH and programmed with an 2X IREF current. It has a 250-k internal pull-up. S0 and S1 inputs are sensed on power-up and then internally latched. Afterwards the pins are 3V 48-MHz clocks. Input select pin. See Table 1 on page 1. It has a 250-k internal Pull-up Crystal Buffer output pin. Connects to a crystal only. When an external signal other than a crystal is used or when in Test mode, this pin is kept unconnected. Crystal Buffer input pin. Connects to a crystal, or an external single ended input clock signal. A buffered output clock of the signal applied at Xin. Typically, 14.31818 MHz. These input select pins configure the Ioh current (and thus the Voh swing amplitude) of the CPU clock output pairs. Each pin has a 250-k internal Pull-up. See Table 6 for current and resistor values. 3.3V power supply pins. 3.3V power supply pins for common supply to the core. Ground pins for common supply to the core. Ground pins. 7,10, 13, 16, 42, 39, 36, 33 8, 11, 14, 17, 41, 38, 35, 32 26 CPU(0:7) CPU(0:7)# IRef P 1 44 3V33 PD# O PU I 3, 4 48 23 22 19 30, 29 48M(0,1), S(0,1) SEL100/133 XOUT XIN REF Mult(0,1) IO PU I O I O I 25, 46 2, 6, 12, 18, 24, 31, 37, 43 5, 9, 15, 21, 28, 34, 40, 47 27, 45 VDDA VDD VSS VSSA P P P P Note: 1. Definition of I/O column mnemonic on pin description table above 1= Input pin, O = output pin, P = power supply pin, PU = indicates that a bidirectional pin contains pull-up resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD designation are guaranteed to be seen as a logic 0 level if no external level setting circuitry is present at power up. Rev 1.0, November 24, 2006 Page 2 of 12 CY28159 Table 3. Group Offset Specifications Group CPU to 3V33 CPU to REF Offset No requirement No requirement Comments Table 4. Group Limits and Parameters (Applicable to all settings: Sel133/100#=x) Output Name CPU[(0:7)#] REF 3V33 Max Load See Figure 1 20 pF 30 pF Test Load Configuration The following shows test load configurations for the different Host Clock Outputs.(MULTsel1 = 0, MULTsel0 =1 TPCB VDD CPUT 2pF Measurement Point MULTSEL TPCB CPUT# 2pF Measurement Point Figure 1. 0.7V Test Load Termination Output Under Test Probe CLOAD Figure 2. Lumped Load Termination Rev 1.0, November 24, 2006 Page 3 of 12 CY28159 3.3V signals tD C - 3.3V 2.4V 1.5V 0.4V 0V Tr Tf Figure 3. 3.3V Measurement Points Rev 1.0, November 24, 2006 Page 4 of 12 CY28159 Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic InterTable 5. Spectrum Spreading Selection Table Unspread Frequency in MHz F Min(MHz) 100 133.3 200 99.5 132.66 199.5 Spread Spectrum Parameter Downspreading F Center(MHz) 99.75 132.67 199.75 F Max(MHz) 100 133 200 Spread (%) –0.5% –0.5% –0.5% ference radiation generated from repetitive digital signals mainly clocks. For a detailed explanation of Spread Spectrum Clock Generation. Power Management Functions Table 6. Host Swing Select Functions[2] Multsel0 0 0 0 0 1 1 1 1 MultSel1 0 0 1 1 0 0 1 1 Board Target Trace/TermZ 60 Ohms 50 Ohms 60 Ohms 50 Ohms 60 Ohms 50 Ohms 60 Ohms 50 Ohms Reference Rr, Iref = Vdd(3*Rr) Note 3 Rf = 475 1%, Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Rr = 475 1%,Iref = 2.32 mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh@Z, Iref = 2.32 mA 07V@60 0.59V @ 50 0.85V @ 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50 Notes: 2. The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations. 3. Rr refers to the resistance placed in series with the Iref input and VSS. Rev 1.0, November 24, 2006 Page 5 of 12 CY28159 Buffer Characteristics Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained elsewhere in this datasheet. The following parameters are used to specify output buffer characteristics: 1. Output impedance of the current mode buffer circuit - Ro (see Figure 4) 2. Minimum and maximum required voltage operation range of the circuit - Vop (see Figure 4). 3. Series resistance in the buffer circuit - Ros (see Figure 4) 4. .Current accuracy at given configuration into nominal test load for given configuration VDD3 (3.3V +/- 5%) Ro Iout Ros 0V Iout 1.2V Vout = 1.2V max Vout Figure 4. Table 7. Host Clock (HSCL) Buffer Characteristics Characteristics Ro Ros Vout Unspecified N/A Minimum 3000 Ohms (recommended) N/A Unspecified 1.2 Volt The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is ±7% as shown in the table current accuracy. Maximum Iout is selectable depending on implementation. The parameters above supply to all configurations. Vout is the voltage at the pin of the device. Rev 1.0, November 24, 2006 Page 6 of 12 CY28159 Table 8. Current Accuracy Conditions Iout Iout Configuration Load Min. –7% Inom Max. +7% Inom VDD = nominal (3.30V) All combinations of M0, M1 and Rr shown in Nominal test load for Host Swing Select Function, Table 6 on page 5 given configuration VDD = 3.30 ± 5% All combinations of M0, m1 and Rr shown in Nominal test load for –12% Inom +12% Inom Host Swing Select Function, Table 6 on page 5 given configuration Table 9. Buffer Characteristics for REF, 48M(0,1) Parameter IOHmin IOHmax IOLmin IOLmax Trh Tfh Description Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. 3.3V Output Rise Edge Rate 3.3V Output Fall Edge Rate Conditions VOH = VDDmin – 0.5V (2.64V) VOH = VDDmin/2 (1.56V) VOL = 0.4V VOL = VDDmin/2 (1.56V) 3.3V ± 5% @ 0.4V–2.4V 3.3V ± 5% @ 2.4V–0.4V Min. –12 –27 9 26 0.5 0.5 Typ. Max. –53 –92 27 79 2.0 2.0 Unit mA mA mA mA V/ns V/ns Table 10.Buffer Characteristics for 3V33[4] Parameter IOHmin IOHmax IOLmin IOLmax Trh Tfh Description Pull-Up Current Min. Pull-Up Current Max. Pull-Up Current Max. Pull-Down Current Max. 3.3V Output Rise Edge Rate 3.3V Output Fall Edge Rate Conditions VOH = VDDmin – 0.5V (2.64V) VOH = VDDmin/2 (1.56V) VOL = 0.4V VOL = VDDmin/2 (1.56V) 3.3V ± 5% @ 0.4V–2.4V 3.3V ± 5% @ 2.4V–0.4V Min. –11 –30 9 28 1/1 1/1 Typ. Max. –83 –184 38 148 4/1 4/1 Unit mA mA mA mA V/ns V/ns Note: 4. Inom refers to the expected current based on the configuration of the device. Rev 1.0, November 24, 2006 Page 7 of 12 CY28159 Maximum Ratings[5] Input Voltage Relative to VSS:............................... VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................ –65 C to + 150 C Operating Temperature:.................................... 0 C to +70 C Maximum ESD............................................................. 2000V Maximum Power Supply: ................................................ 5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field. However, precautions should be take to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range. VSS < (VIN or VOUT)< VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters (VDD = VDDA = 3.3V±5%, TA= 0°C to +70°C) Parameter VIL1 VIH1 IIL IIH IIL IIH Ioz Idd Isdd Cin Cout Lpin Cxtal Txs Rpi Description Input Low Voltage Input High Voltage Input Low Current (@VIN–VDD) Input High Current (@VIN–VDD) nput Low Current (@VIN–VSS) Input High Current (@VIN–VSS) Three-State leakage current Static Supply Current Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Crsytal Startup Time Internal Pull-up and Pull-down Resistor Value[7] Measured from Pin to Ground. From stable 3.3V power supply 200 250 34 36 PwrDwn = Low 133 MHz CPU[8] For internal pull-down resistors[6] For internal pull-up resistors[6] Note 6 2.0 –16 0 0 4 16 10 80 200 5 6 7 38 40 500 k –4 5 Conditions Min. Typ. Max. 0.8 Unit Vdc Vdc A A A A A mA mA pF pF nH pH S Notes: 5. The voltage on any input or I/O pin canno t exceed th power pin during power-up. Power supply sequencing is NOT required. 6. Applicable to input signals: Sel100/133, Sel(0:1)), Spread#, PWRDN#, Mult(0:1) 7. Although internal pull-up or pull-down resistors have a typical value of 250k, this value may vary between 200k and 500k. 8. All outputs loaded as per Table 4. Rev 1.0, November 24, 2006 Page 8 of 12 CY28159 AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) Symbol Description 133 MHz Host Min. CPU 7.35 175 Max. 7.65 700 100 150 Voh + 0.2 –0.2 45%Voh 45 33MHz 15.0 5.25 5.05 0.5 45 REF 69.8412 1.0 45 48MHz 45 20.8299 1.0 20 1.0 1.0 10.0 10.0 3 2.0 300 55 71.0 4.0 1000 55 55 20.8333 4.0 500 20 1.0 1.0 10.0 10.0 3 ns ns ms 16 16 45 45 20.8299 1.0 55%Voh 55 16.0 45%Voh 45 15.0 5.25 5.05 0.5 45 69.8413 1.0 2.0 300 55 71.0 4.0 1000 55 55 20.8333 4.0 500 100 MHz Host Min. 9.85 175 Max. 10.2 700 100 150 Voh + 0.2 -0.2 55%Voh 55 15.2 Unit Notes TPeriod Tr/Tf TSKEW1 TCJJ Vover Vunder Vcrossover Tduty Tperiod THIGH TLOW Tr/Tf TCCJ Tduty Tperiod Tr/Tf TCCj Tduty TDC Tperiod Tr/Tf TCCJ Zout tpZL, tpZH tpLZ, tpZH tstable CPU(0:7), (0:7)#) Period CPU[(0:7), (0:7)#] Rise and Fall Times Skew from Any CPU Pair to Any CPU Pair CPU[(0:7), (0:7)#] Cycle to Cycle Jitter CPU[(0:7), (0:7)#] Overshoot CPU[(0:7), (0:7)#] Undershoot CPU(0:7), to CPU(0:7)# Crossover Point Duty Cycle 3V33 Period 3V33 High Time 3V33 Low Time 3V33 Rise and Fall Times 3V33 Cycle to Cycle Jitter Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Duty Cycle 48MHz(0,1) Duty Cycle 48MHz(0.1) Period 48MHz(0,1) Rise and Fall Times 48MHz(0,1) Cycle to Cycle Jitter 48MHz Buffer Output Impedance Output Enable Delay (all outputs) Output Disable Delay (all outputs) All Clock Stabilization from Power-up ns ps ps ps V V V % ns ns ns ns ps % nS nS pS % % ns ps ps 10,12 10,11 10,12,13 10,12,13 10,17 10,17 9, 10,12 10,12 10,12 10,14 10,15 10,11 10,12,13 10,12 10,12 10,11 10,12 10,12 10,12 10,12 10,11 10,12 Notes: 9. This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1 s duration, with a crystal center frequency of 14.31818 MHz. 10. All outputs loaded as per Table 4, see Figure 2. 11. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for CPU[(0:7), (0:7)#] signals (see Figure 3). 12. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figure 3). 13. This measurement is applicable with Spread ON or Spread OFF. 14. Probes are placed on the pins, and measurements are acquired at 2.4V (see Figure 3). 15. Probes are placed on the pins, and measurements are acquired at 0.4V. (seeFigure 3). 16. As this function is available through SEL(0,1), therefore, the time specified is guaranteed by design. 17. Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge. Rev 1.0, November 24, 2006 Page 9 of 12 CY28159 Sample Layout +3.3V Supply FB FB VDDQ3 0.005 F VDDQ3A * C3 G C1 10 F 0.005 F C2 G G G G G G G 1G 2 3 4 5G 6V 7G 8 9 10 11 G 12 V 13 G 14 15 G 16 17 G 18 V 19 G 20 21 G 22 23 G 24 V G 48 47 V46 G 45 44 V 43 G 42 41 40 39 G 38 V 37 G 36 35 G 34 33 G 32 V 31 G 30 29 G 28 27 G 26 V 25 G * G CY28159 @ 100 MHz) G G G * FB = Dale ILB1206 - 300 (300 Cermaic Caps C1 & C3 = 10–22 µF G = VIA to GND plane layer C2 & C4 = 0.005 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F cermamic. Low ESR Rev 1.0, November 24, 2006 Page 10 of 12 CY28159 Ordering Information Part Number CY28159PVC CY28159PVCT CY28159ZC CY28159ZCT Package Type 48-Pin SSOP 48-Pin SSOP - Tape and Reel 48-Pin TSSOP 48-Pin TSSOP - Tape and Reel Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Package Drawing and Dimensions 48-Lead Shrunk Small Outline Package O48 51 85061 *C Rev 1.0, November 24, 2006 Page 11 of 12 CY28159 Package Drawing and Dimensions (continued) 48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 24, 2006 Page 12 of 12