CY28324

CY28324 FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel® CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale (845) and Brookdale - G Pentium® 4 Chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when Watchdog Timer time-out • Capable of generating system RESET after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte read/write and block read/write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP CPU x2 3V66 x4 PCI x 10 REF x2 48M x1 24_48M x1 Block Diagram X1 X2 Pin Configuration VDD_REF REF0:1 XTAL OSC PLL 1 SSOP-48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/MULTSEL0* GND_REF VDD_MREF 3VMREF/CPU_STP#* 3VMREF#/PCI_STP#* GND_MREF PWR_DWN# CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU IREF VDD_CORE GND_CORE VDD_3V66 3V66_0 3V66_1 GND_3V66 3V66_2 3V66_3 SCLK SDATA PLL Ref Freq Divider Network Stop Clock Control *FS0:4 VTT_PWRGD# *CPU_STP# *MULTSEL0:1 PWR_DWN# Stop Clock Control *PCI_STP# *MULTSEL1/REF1 VDD_REF X1 X2 GND_PCI *FS2/PCI_F0 *FS3/PCI_F1 VDD_MREF 3VMREF, 3VMREF# *MODE/PCI_F2 VDD_PCI VDD_3V66 *FS4/PCI0 3V66_0:3 PCI1 PCI2 GND_PCI VDD_PCI PCI3 PCI_F0:2 PCI4 PCI0:6 PCI5 PCI6 VDD_PCI VTT_PWRGD# RST# GND_48MHz *FS0/48MHz *FS1/24_48MHz VDD_48MHz VDD_48MHz VDD_CPU CPU0:1, CPU0:1# 48MHz ~ CY28324 PLL2 24_48MHz 2 Note: 1. Signals marked with ‘*’ have internal pull-up resistor. SDATA SCLK SMBus Logic RST# Intel and Pentium are registered trademarks of Intel Corporation. Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 21 www.SpectraLinear.com CY28324 Pin Definitions Pin Name X1 Pin No. 3 Pin Type I Pin Description Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = IOH is 4 x IREF 01 = IOH is 5 x IREF 10 = IOH is 6 x IREF 11 = IOH is 7 x IREF X2 REF0/MULTSEL0 4 48 O I/O REF1/MULTSEL1 1 I/O Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = IOH is 5 x IREF 10 = IOH is 6 x IREF 11 = IOH is 7 x IREF CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through the serial input interface. Memory Reference Clock/CPU Output Control: The function of this pin is controlled by the Mode input pin. When Mode input is sampled HIGH during power-on reset, this pin will be configured as 3VMREF output. When Mode input is sampled LOW during power-on reset, this pin will be configured as CPU_STP# input. 3VMREF is a 3.3V output running at half the frequency of the CPU output clock. CPU_STP# is a 3.3V LVTTL compatible input that disables CPU0, CPU0#, CPU1 and CPU1# outputs. Memory Reference Clock/PCI Output Control: The function of this pin is controlled by the Mode input pin. When Mode input is sampled HIGH during power-on reset, this pin will be configured as 3VMREF# output. When Mode input is sampled LOW during power-on reset, this pin will be configured as PCI_STP# input. 3VMREF# is a 3.3V output running at half the frequency of the CPU output clock. 3VMREF# is 180 degree out of phase with respect to 3VMREF. PCI_STP# is a 3.3V LVTTL-compatible input that disables PCI0:6 outputs. 66-MHz Clock Outputs: 3.3V fixed 66-MHz clock. Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 2/Mode Selection: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine the functions of 3VMREF/CPU_STP# and 3VMREF#/PCI_STP#. When Mode input is sampled HIGH during power-on reset, 3VMREF/CPU_STP# and 3VMREF#/PCI_STP# will be configured as 3VMREF and 3VMREF# output, respectively. When Mode input is sampled LOW during power-on reset, 3VMREF/CPU_STP# and 3VMREF#/PCI_STP# will be configured as CPU_STP# and PCI_STP# input, respectively. CPU0:1, CPU0:1# 3VMREF/CPU_STP # 41, 38, 40, 37 45 O I/O 3VMREF#/PCI_STP # 44 I/O 3V66_0:3 PCI_F0/FS2 31, 30, 28, 27 6 O I/O PCI_F1/FS3 7 I/O PCI_F2/Mode 8 I/O Rev 1.0, November 20, 2006 Page 2 of 21 CY28324 Pin Definitions(continued) Pin Name PCI0/FS4 Pin No. 10 Pin Type I/O Pin Description PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI Clock Output 1 to 6: 3.3V PCI clock outputs. 48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for USB host controller in Intel 845 (Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used as the VCH reference clock. 24- or 48-MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used as the reference clock for both USB host controller and SIO devices. We recommend system designer to configure this output as 48 MHz and “HIGH Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively. Power Down Control: 3.3V LVTTL-compatible input that places the device in power down mode when held LOW. SMBus Clock Input: Clock pin for serial interface. SMBus Data Input: Data pin for serial interface. System Reset Output: Open-drain system reset output. PCI1:6 48MHz/FS0 11, 12, 14, 15, 16, 17 22 O I/O 24_48MHz/FS1 23 I/O PWR_DWN# SCLK SDATA RST# 42 26 25 20 I I I/O O (opendrain) I I IREF VTT_PWRGD# 35 19 Current Reference for CPU Output: A precision resistor is attached to this pin, which is connected to the internal current reference. Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input. VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4, MODE and MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. VDD_REF, VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU VDD_MREF GND_PCI, GND_48MHz, GND_3V66, GND_CPU, GND_MREF, GND_REF, VDD_CORE GND_CORE 2, 9, 18, 24, 32, 39, 46 P 5, 13, 21, 29, 36, 43, 47 G Ground Connection: Connect all ground pins to the common system ground plane. 34 33 P G 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. Analog Ground Connection: Ground for core logic, PLL circuitry. Rev 1.0, November 20, 2006 Page 3 of 21 CY28324 Swing Select Functions MULTSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MULTSEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 50 60 50 60 50 60 50 60 50 60 50 60 50 60 50 60 Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Output Current IOH = 4*IREF IOH = 4*IREF IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 7*IREF IOH = 7*IREF IOH = 4*IREF IOH = 4*IREF IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 7*IREF IOH = 7*IREF VOH @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 60 0.47V @ 50 0.56V @ 60 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60 Rev 1.0, November 20, 2006 Page 4 of 21 CY28324 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 2 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 6:0 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be ‘0000000’. Descriptions Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not acknowledge Stop Block Read Protocol Description Rev 1.0, November 20, 2006 Page 5 of 21 CY28324 Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Data byte from slave – 8 bits Not acknowledge Stop Byte Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Data Byte Configuration Map Data Byte 0 Bit Bit 7 Bit 6 Bit 5 Pin# ---Name Spread Select2 Spread Select1 Spread Select0 ‘000’ = OFF ‘001’ = Reserved ‘010’ = Reserved ‘011’ = Reserved ‘100’ = ± 0.25% ‘101’ = – 0.5% ‘110’ = ±0.5% ‘111’ = ±0.38% SW Frequency selection bits. See Table 4. Description Power-On Default 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ------ SEL4 SEL3 SEL2 SEL1 SEL0 0 0 0 0 0 Pin# 38, 37 41, 40 22 23 27 28 30 31 Name CPU1, CPU1# CPU0, CPU0# 48MHz 24_48MHz 3V66_3 3V66_2 3V66_1 3V66_0 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Power-On Default 1 1 1 1 1 1 1 1 Rev 1.0, November 20, 2006 Page 6 of 21 CY28324 Data Byte 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# -17 16 15 14 12 11 10 Reserved PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description Power-On Default 0 1 1 1 1 1 1 1 Data Byte 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 4 Bit Bit 7 Pin# -Name MULTSEL_Override Pin Description This bit control the selection of IREF multiplier. 0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins 1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6]. IREF multiplier 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF Reserved Reserved Reserved 0 = Not free running 1 = Free running; not affected by CPU_STOP# 0 = Not free running 1 = Free running; not affected by CPU_STOP# Power-On Default 0 Pin# 8 7 6 -44, 45 -1 48 PCI_F2 PCI_F1 PCI_F0 Reserved 3VMREF#, 3VMREF Reserved REF1 REF0 Name (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) Pin Description Power-On Default 1 1 1 0 1 0 1 1 Bit 6 Bit 5 --- SW_MULTSEL1 SW_MULTSEL0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ------ Reserved Reserved Reserved CPU1 Stop Control CPU0 Stop Control Reserved Reserved Reserved 0 0 Rev 1.0, November 20, 2006 Page 7 of 21 CY28324 Data Byte 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 10 7 6 23 22 --23 Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input FS_Override Reserved SEL 48MHZ 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings Reserved 0 = 24 MHz 1 = 48 MHz Pin Description Latched FS[4:0] inputs. These bits are read only. Power-On Default X X X X X 0 0 0 Data Byte 6 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor _ID0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Pin Description Power-On Default 0 0 0 0 1 0 0 0 Data Byte 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-On Default 0 0 0 0 0 0 0 0 Rev 1.0, November 20, 2006 Page 8 of 21 CY28324 Data Byte 8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------Reserved Reserved WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 WD_PRE_SCALER Name Reserved Reserved These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescalar is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec. to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 0 = 150 ms 1 = 2.5 sec Pin Description Power-On Default 0 0 1 1 1 1 1 0 Data Byte 9 Bit Bit 7 Pin# -Name 48MHz_DRV Pin Description 48MHz & 24_48MHz clock output drive strength 0 = Normal 1 = High Drive (Recommend to set to high drive if this output is being used to drive both USB and SIO devices in Intel® Brookdale - G platforms) PCI clock output drive strength 0 = Normal 1 = High Drive 3V66 clock output drive strength 0 = Normal 1 = High Drive This bit will enable the generation of a Reset pulse when a Watchdog Timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = Time-out occurred (READ); Clear WD_TO_STATUS (WRITE) 0 = Stop and reload Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: CY28324 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28324 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28324 from its recovery frequency mode by clearing the WD_EN bit. Reserved Power-On Default 0 Bit 6 -- PCI_DRV 0 Bit 5 -- 3V66_DRV 0 Bit 4 -- RST_EN_WD 0 Bit 3 -- RST_EN_FC 0 Bit 2 -- WD_TO_STATUS 0 Bit 1 -- WD_EN 0 Bit 0 -- Reserved 0 Rev 1.0, November 20, 2006 Page 9 of 21 CY28324 Data Byte 10 Bit Bit 7 Bit 6 Bit 5 Pin# 10 7 6 Name CPU_Skew2 CPU_Skew1 CPU_Skew0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Reserved PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps 3v66 skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Pin Description Power-On Default 0 0 0 Bit 4 Bit 3 Bit 2 23 22 -- Reserved PCI_Skew1 PCI_Skew0 0 0 0 Bit 1 Bit 0 --- 3V66_Skew1 3V66_Skew0 0 0 Data Byte 11 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be use to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-On Default 0 0 0 0 0 0 0 0 Data Byte 12 Bit Bit 7 Pin# -Name ROCV_FREQ_SEL Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] Power-On Default 0 Rev 1.0, November 20, 2006 Page 10 of 21 CY28324 Data Byte 12 (continued) Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# -------Name ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0 Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be use to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-On Default 0 0 0 0 0 0 0 Data Byte 13 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-On Default 0 0 0 0 0 0 0 0 Data Byte 14 Bit Bit 7 Pin# -Name Pro_Freq_EN Pin Description Programmable output frequencies enabled 0 = Disabled 1 = Enabled If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-On Default 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -------- CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 0 0 0 0 0 0 0 Data Byte 15 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Pin# -----Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Pin Description Power-On Default 0 0 0 0 0 Rev 1.0, November 20, 2006 Page 11 of 21 CY28324 Data Byte 15 (continued) Bit Bit 2 Bit 1 Bit 0 Pin# ---Reserved Vendor Test Mode Vendor Test Mode Name Reserved Reserved. Write with “1” Reserved. Write with “1” Pin Description Power-On Default 0 1 1 Data Byte 16 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 17 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-On Default 0 0 0 0 0 0 0 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-On Default 0 0 0 0 0 0 0 0 Rev 1.0, November 20, 2006 Page 12 of 21 CY28324 Table 4. Frequency Selection Table Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 102.0 105.0 108.0 111.0 114.0 117.0 120.0 123.0 126.0 130.0 136.0 140.0 144.0 148.0 152.0 156.0 160.0 164.0 166.6 170.0 175.0 180.0 185.0 190.0 66.8 100.2 133.6 200.4 66.6 100.0 200.0 133.3 3V66 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 63.0 65.0 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 66.6 68.0 70.0 72.0 74.0 76.0 66.8 66.8 66.8 66.8 66.6 66.6 66.6 66.6 PCI 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 31.5 32.5 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 33.3 34.0 35.0 36.0 37.0 38.0 33.4 33.4 33.4 33.4 33.3 33.3 33.3 33.3 Output Frequency PLL Gear Constants (G) 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 Rev 1.0, November 20, 2006 Page 13 of 21 CY28324 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency in the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. Table 5. Register Summary Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = Disabled (Default) 1 = Enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If the FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. 0 = Stop and re-load Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = Time-out occurred (READ); Clear WD_TO_STATUS (WRITE) The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog Timer before they attempt to make a frequency change. If the system hangs and a Watchdog Timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. FS_Override CPU_FSEL_N, CPU_FSEL_M ROCV_FREQ_SEL ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] WD_EN WD_TO_STATUS Rev 1.0, November 20, 2006 Page 14 of 21 CY28324 Table 5. Register Summary(continued) Name WD_TIMER[4:0] Description These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N + 3) and (M + 3) need to be greater than “1” [(N + 3)/(M + 3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. WD_PRE_SCALER RST_EN_WD RST_EN_FC Program the CPU output frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 50 MHz–129 MHz 130 MHz–248 MHz Gear Constants 48.00741 48.00741 Fixed Value for M-Value Register 93 45 Range of N-Value Register for Different CPU Frequency 97–255 127–245 Rev 1.0, November 20, 2006 Page 15 of 21 CY28324 Maximum Ratings[1] (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Input Voltage............................................ –0.5V to VDD + 0.5 Storage Temperature (Non-Condensing) ....–65 C to +150 C Max. Soldering Temperature (10 sec) ....................... +260 C Junction Temperature................................................ +150 C Package Power Dissipation............................................... 1 Static Discharge Voltage ........................................................ (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Over which Electrical Parameters are Guaranteed Parameter VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_48 MHz, VDD_CPU, TA Cin CXTAL CL Description 3.3V Supply Voltages Operating Temperature, Ambient Input Pin Capacitance XTAL Pin Capacitance Max. Capacitive Load on 48 MHz, REF PCICLK, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 0 Max. 3.465 70 5 22.5 20 30 14.318 MHz Unit V C pF pF pF f(REF) Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads 48 MHz, REF, 3V66, 3VMREF PCI 48 MHz, REF, 3V66, 3VMREF PCI 0 < VIN < VDD 0 < VIN < VDD CPU For IOH =6*IRef Configuration REF, 48 MHz, 3VMREF 3V66, 3VMREF, PCI IOL Low-level Output Current REF, 3VMREF, 48 MHz 3V66, PCI, 3VMREF IOZ IDD3 IDDPD3 Output Leakage Current 3.3V Shutdown Current Three-state VDD_CORE/VDDQ3 = 3.465V Type X1, VOH = 0.65V Type X1, VOH = 0.74V Type 3, VOH = 1.00V Type 3, VOH = 3.135V Type 5, VOH = 1.00V Type 5, VOH = 3.135V Type 3, VOL = 1.95V Type 3, VOL = 0.4V Type 5, VOL =1.95 V Type 5, VOL = 0.4V 3.3V Power Supply Current VDD_CORE/VDDQ3 = 3.465V, FCPU = 133 MHz 30 38 10 250 20 mA mA mA 29 27 –33 –33 mA –29 –23 IOH = –1 mA IOH = –1 mA IOL = 1 mA IOL = 1 mA –5 –5 12.9 14.9 2.4 2.4 0.4 0.55 5 5 Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V V V V mA mA mA Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Rev 1.0, November 20, 2006 Page 16 of 21 CY28324 - Switching Characteristics[2] Over the Operating Range Parameter t1 t2 t2 t2 t3 t3 t3 t4 t5 t6 t7 t8 t9 t9 t9 t9 All CPU REF, 48 MHz PCI, 3V66, 3VMREF CPU REF, 48 MHz PCI, 3V66, 3VMREF CPU 3V66 [0:3] PCI 3V66, PCI CPU 3V66, 3VMREF 48 MHz PCI REF CPU, PCI CPU CPU CPU Voh Vol Vcrossover CPU CPU CPU Output Description Output Duty Cycle[3] Rise Time Rising Edge Rate Rising Edge Rate Fall Time Falling Edge Rate Falling Edge Rate CPU-CPU Skew 3V66-3V66 Skew PCI-PCI Skew 3V66-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time Rise/Fall Matching Overshoot Undershoot High-level Output Voltage Low-level Output Voltage Crossover Voltage t1A/(t1B) Measured at 20% to 80% of Voh Between 0.4V and 2.4V Between 0.4V and 2.4V Measured at 80% to 20% of Voh Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at Crossover Measured at 1.5V Measured at 1.5V 3V66 leads. Measured at 1.5V Measured at Crossover t8 = t8A – t8B With all outputs running Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B CPU and PCI clock stabilization from power-up Measured with test loads[4, 5] Measured with test loads[5] Measured with test loads[5] Measured with test loads[5] Measured with test Measured with test loads[5] loads[5] –0.2 0.65 0.0 45% of 0.65 0.74 0.05 55% of 0.74 1.5 Test Conditions Min. 45 175 0.5 1.0 175 0.5 1.0 Max. 55 700 2.0 4.0 700 2.0 4.0 150 500 500 3.5 200 250 350 500 1000 3 20% Voh + 0.2 V V V V V Unit % ps V/ns V/ns ps V/ns V/ns ps ps ps ns ps ps ps ps ps ms Notes: 2. All parameters specified with loaded outputs. 3. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 4. Determined as a fraction of 2*(tRP – tRN)/(tRP + tRN) Where tRP is a rising edge and tRN is an intersecting falling edge. 5. The test load is Rs = 33.2 , Rp = 49.9 in test circuit. Switching Waveforms Duty Cycle Timing (Single Ended Output) t1B t1A Rev 1.0, November 20, 2006 Page 17 of 21 CY28324 Switching Waveforms (continued) Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD 0V t2 t3 OUTPUT CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 PCI-PCI Clock Skew PCI PCI t6 Rev 1.0, November 20, 2006 Page 18 of 21 CY28324 Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A Host_b Host t8B Cycle-Cycle Clock Jitter t9A t9B CLK Rev 1.0, November 20, 2006 Page 19 of 21 CY28324 Layout Example FB VDDQ3 0.005 F C4 G G C3 G G G VDDQ3 5 1 2V 3G 4 5G 6 7 8G 9V 10 G 11 12 13 G 14 15 16 17 G 18 V 19 20 21 G 22 23 24* G 48 47 V 46 G 45 44 G 43 42 41 G 40 V 39 G 38 37 G 36 35 V 34 G 33 V 32 31 30 G 29 28 27 26 G 25 G G G CY28324 G G G C5 G G C6 FB = Dale ILB1206 - 300 (300 Cermaic Caps C3 = 10–22 G = VIA to GND plane layer F @ 100 MHz) C4 = 0.005 F C5 = 10 F C6 = 0.1 F V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 Rev 1.0, November 20, 2006 Page 20 of 21 CY28324 Ordering Information Ordering Code CY28324PVC Package Name O48 Package Type 48-pin Small Shrunk Outline Package (SSOP) Operating Range Commercial Package Diagram 48-Lead Shrunk Small Outline Package O48 51-85061-B While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 21 of 21