CY28325OC-3

CY28325-3 FTG for VIA™ Pentium 4™ Chipsets Features • Spread Spectrum Frequency Timing Generator for VIA PT/M 266-800 Pentium 4 Chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Selectable hardware or software-programmed clock frequency when Watchdog Timer time-out • Capable to generate system RESET after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus Byte Read/Write and Block Read/Write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable-drive strength support • Programmable-output skew support • Three copies AGP Clocks • Power management control inputs • Available in 48-pin SSOP CPU x3 AGP x3 PCI x9 REF x1 APIC x2 48M x1 24_48M x1 Block Diagram X1 X2 Pin Configuration VDD_REF REF [1] XTAL OSC PLL 1 SSOP-48 *FS4/REF VDD_REF GND_REF X1 X2 VDD_48MHz *FS3/48MHz *FS2/24_48MHz GND_48MHz *FS0/PCI_F *FS1/PCI1 *MULT_SEL1/PCI2 GND_PCI PCI3 PCI4 VDD_PCI PCI5 PCI6 PCI7 GND_PCI PCI8 *PD# AGP0 VDD_AGP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_APIC GND_APIC APIC0 APIC1 GND_CPU VDD_CPU_CS(2.5V) CPUT_CS_F CPUC_CS_F CPUT_0 CPUC_0 VDD_CPU(3.3V) IREF GND_CPU CPUT_1 CPUC_1 VTT_PWRGD# CPU_STOP#* PCI_STOP#* RST# SDATA SCLK AGP2 AGP1 GND_AGP PLL Ref Freq Divider Network Stop Clock Control VDD_CPU_CS (2.5V) CPUT_CS, CPUC_CS VDD_CPU (3.3V) CPUT_0,1, CPUC_0,1 *(FS0:4) VTT_PWRGD# *CPU_STOP# *MULTSEL1 ~ VDD_APIC APIC0:1 VDD_AGP AGP0:2 CY28325-3 VDD_PCI PCI_F PD# Stop Clock Control PCI1:8 *PCI_STOP# PLL2 VDD_48MHz 48MHz 24_48MHz 2 SDATA SCLK SMBus Logic RST# Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors. Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 18 www.SpectraLinear.com CY28325-3 Pin Definitions Pin Name X1 No. 4 Type I Description Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock Output/Frequency Select 4: 3.3V 14.318-MHz output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. CPU Clock Outputs for Chipset: Frequency is set by the FS0:4 inputs or through serial input interface. APIC Clock Output: APIC clock outputs running at half of PCI output frequency. AGP Clock Output: 3.3V AGP clock. Free-running PCI Output 1/Frequency Select 1: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI Output 1 /Frequency Select 1: 3.3V PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI Output 2/Current Multiplier Selection 1: 3.3V PCI output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL definitions are as follows: MULTISEL 0 = Ioh is 4 × IREF 1 = Ioh is 6 × IREF PCI Clock Output 3 to 8: 3.3V PCI clock outputs. 48-MHz Output/Frequency Select 3: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. 24- or 48-MHz Output/Frequency Select 2: 3.3V fixed 24- or 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. CPU Output Control: 3.3V LVTTL-compatible input that disables CPUT_CS, CPUC_CS, CPUT_0:1 and CPUC_0:1. PCI Output Control: 3.3V LVTTL-compatible input that disables PCI1:8. Power-down Control: 3.3V LVTTL-compatible input that places the device in power down mode when held LOW. SMBus Clock Input: Clock pin for serial interface. SMBus Data Input: Data pin for serial interface. X2 REF/FS4 5 1 O I/O CPUT_0:1 CPUC_0:1 CPUT_CS_F CPUC_CS_F APIC0:1 AGP 0:2 PCI_F/FS0 40, 39, 35, 34 42, 41 46, 45 23, 26, 27 10 O O O O I/O PCI1/FS1 11 I/O PCI2/MULTSEL1 12 I/O PCI3:8 48MHz/FS3 14, 15, 17, 18, 19, 21 7 O I/O 24_48MHz/FS2 8 I/O CPU_STOP# PCI_ST0P# PD# SCLK SDATA RST# IREF 32 31 22 28 29 30 37 I I I I I/O O System Reset Output: Open-drain system reset output. (open-drain) I Current Reference for CPU output: A precision resistor is attached to this pin, which is connected to the internal current reference. Rev 1.0, November 21, 2006 Page 2 of 18 CY28325-3 Pin Definitions (continued) Pin Name VTT_PWRGD# No. 33 Type I Description Power-good from Voltage Regulator Module (VRM): 3.3V LVTTL input. VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and MULTSEL inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. 2.5V Power Connection: Power supply for CPU_CS outputs buffers and APIC output buffers. Connect to 2.5V. 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. VDD_CPU_CS, VDD_APIC VDD_REF, VDD_48MHz, VDD _PCI, VDD_AGP, VDD_CPU GND_REF GND_48MHz, GND_PCI, GND_AGP, GND_CPU, GND_APIC 43, 48 2, 6, 16, 24, 38 P P 3, 9, 13, 20, 25, 36, 44, 47 G Ground Connection: Connect all ground pins to the common system ground plane. Table 1. Frequency Selection Table Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 102.0 105.0 108.0 111.0 114.0 117.0 120.0 123.0 126.0 130.0 136.0 140.0 144.0 148.0 152.0 156.0 160.0 164.0 166.6 170.0 175.0 180.0 AGP 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 63.0 65.0 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 66.6 68.0 70.0 72.0 PCI 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 31.5 32.5 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 33.3 34.0 35.0 36.0 APIC 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 18.0 18.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 16.7 17.0 17.5 18.0 Output Frequency PLL Gear Constants (G) 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 Rev 1.0, November 21, 2006 Page 3 of 18 CY28325-3 Table 1. Frequency Selection Table (continued) Input Conditions FS4 SEL4 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 CPU 185.0 190.0 100.9 133.9 200.5 166.8 100.0 133.3 200.0 166.7 AGP 74.0 76.0 67.3 67.0 66.8 66.7 66.6 66.6 66.6 66.7 PCI 37.0 38.0 33.6 33.5 33.4 33.3 33.3 33.3 33.3 33.3 APIC 18.5 19.0 16.8 16.7 16.7 16.7 16.7 16.7 16.7 16.7 Output Frequency PLL Gear Constants (G) 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 Swing Select Functions MultSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MultSEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 50 60 50 60 50 60 50 60 50 60 50 60 50 60 50 Ohm 60 Ohm Reference R, IREF = VDD/(3*Rr) Output Current IOH = 4*Iref IOH = 4*Iref IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 7*Iref IOH = 7*Iref IOH = 4*Iref IOH = 4*Iref IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 7*Iref IOH = 7*Iref VOH @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 60 0.47V @ 50 0.56V @ 60 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60 Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32mA Rr = 475 1%, IREF = 2.32mA Rev 1.0, November 21, 2006 Page 4 of 18 CY28325-3 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). T Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 Bit '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave ...................... Data Byte (N–1) –8 bits Acknowledge from slave Data Byte N –8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 Bit '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte N from slave – 8 bits Acknowledge from master Stop Block Read Protocol Description Rev 1.0, November 21, 2006 Page 5 of 18 CY28325-3 Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Acknowledge from master Stop Byte Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Rev 1.0, November 21, 2006 Page 6 of 18 CY28325-3 Data Byte Configuration Map Data Byte 0 Bit 7 6 5 4 3 2 1 0 Data Byte 1 Bit 7 6 5 4 Pin# – – – – Name Reserved Spread Select2 Spread Select1 Spread Select0 Reserved “000” = OFF “001” = Reserved “010” = Reserved ‘011” = Reserved “100“ = ± 0.25% “101“ = – 0.5% “110“= ±0.5% “111“ = ±0.38% 3 2 1 0 42, 41 35, 34 40, 39 – CPUT_CS, CPUC_CS (Active/Inactive) CPUT_1, CPUC_1 CPUT_0, CPUC_0 CPU_CS_F STOP Control (Active/Inactive) (Active/Inactive) 1 = CPUT_CS_F and CPUC_CS_F are Free-running outputs 0 = CPUT_CS_F and CPUC_CS_F will be disabled when CPU_STOP# is active 1 1 1 1 Description Power-on Default 0 0 0 0 Pin# – – – – – – – – SEL2 SEL1 SEL0 FS_Override SEL4 SEL3 Reserved Name Reserved Reserved SW Frequency selection bits. Refer to Frequency Selection Table SW Frequency selection bits. Refer to Frequency Selection Table SW Frequency selection bits. Refer to Frequency Selection Table 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings SW Frequency selection bits. Refer to Frequency Selection Table SW Frequency selection bits. Refer to Frequency Selection Table Reserved Description Power-on Default 0 0 0 0 0 0 0 0 Data Byte 2 Bit 7 6 5 4 3 2 1 0 Data Byte 3 Bit 7 Pin# – Reserved Name Reserved Pin Description Power-on Default 0 Pin# 21 19 18 17 15 14 12 11 PCI8 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Name Pin Description 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled Power-on Default 1 1 1 1 1 1 1 1 Rev 1.0, November 21, 2006 Page 7 of 18 CY28325-3 Data Byte 3 Bit 6 5 4 3 2 1 0 Data Byte 4 Bit 7 6 Pin# – – Name PCI_Skew1 PCI_Skew0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 0 = 150 ms 1 = 2.5 sec Pin Description Power-on Default 0 0 Pin# 8 7 8 10 27 26 23 Name SEL_48MHZ 48MHz 24_48MHz PCI_F AGP2 AGP1 AGP0 0 = 24 MHz 1 = 48 MHz 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled 1 = Enabled, 0 = Disabled Pin Description Power-on Default 0 1 1 1 1 1 1 5 4 3 2 1 0 Data Byte 5 Bit 7 – – – – – – WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 WD_PRE_SCALER 1 1 1 1 1 0 Pin# 7 Name 48MHz_DRV Pin Description 48-MHz clock output drive strength 0 = Normal 1 = High Drive 24_48 MHz clock output drive strength 0 = Normal 1 = High Drive (Active/Inactive) (Active/Inactive) IREF multiplier 00 = Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF (Active/Inactive) Power-on Default 1 6 8 24_48MHz_DRV 1 5 4 3 2 45 46 – – APCI1 APIC0 SW_MULTSEL1 SW_MULTSEL0 1 1 0 0 1 0 1 – REF 1 0 MULTSEL_Override This bit control the selection of IREF multipler. 0 = HW control; IREF multiplier is determined by MULTSEL1 input pin 1 = SW control; IREF multiplier is determined by SW_MULTSEL[0:1] Data Byte 6 Bit 7 6 Pin# – – Reserved Reserved Name Reserved Reserved Pin Description Power-on Default 1 1 Rev 1.0, November 21, 2006 Page 8 of 18 CY28325-3 Data Byte 6 (continued) Bit 5 4 3 2 1 0 Data Byte 7 Bit 7 6 5 4 3 2 1 0 Data Byte 8 Bit 7 6 5 4 3 2 1 0 Data Byte 9 Bit 7 6 Pin# – – Name Reserved PCI_DRV Reserved PCI clock output drive strength 0 = Low Drive 1 = High Drive AGP clock output drive strength 0 = Low Drive 1 = High Drive This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Pin Description Power-on Default 0 0 Pin# – – – – – – – – Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress’s Vendor ID. This bit is Read-only. Bit[2] of Cypress’s Vendor ID. This bit is Read-only. Bit[1] of Cypress’s Vendor ID. This bit is Read-only. Bit[0] of Cypress’s Vendor ID. This bit is Read-only. Pin Description Power-on Default 0 0 0 0 1 0 0 0 Pin# – – – – – – – – Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-on Default 1 1 1 1 1 1 1 1 Pin# – – – – – – Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-on Default 1 1 1 1 1 1 5 – AGP_DRV 0 4 – RST_EN_WD 0 3 – RST_EN_FC 0 Rev 1.0, November 21, 2006 Page 9 of 18 CY28325-3 Data Byte 9 (continued) Bit 2 Pin# – Name WD_TO_STAT US WD_EN Pin Description Watchdog Timer Time-out Status Bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note:CY28325-3 will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28325-2 will not respond to any attempt to change the output frequency via the SMBus control bytes. System software can unlock the CY28325-3 from its recovery frequency mode by clearing the WD_EN bit. Reserved Power-on Default 0 1 – 0 0 Data Byte 10 Bit 7 6 5 – Reserved 0 Pin# – – – Name CPU_CS_F Skew2 CPU_CS_F Skew1 CPU_CS_F Skew0 Pin Description CPU_CS_F Skew Control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps CPUT_0:1 and CPUC_0:1 Skew Control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps AGP Skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Power-on Default 0 0 0 4 3 2 – – – CPU_Skew2 CPU_Skew1 CPU_Skew0 0 0 0 1 0 – – AGP_Skew1 AGP_Skew0 0 0 Data Byte 11 Bit 7 6 5 4 3 2 1 0 Pin# – – – – – – – – Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default 0 0 0 0 0 0 0 0 Rev 1.0, November 21, 2006 Page 10 of 18 CY28325-3 Data Byte 12 Bit 7 Pin# – Name ROCV_FREQ_SEL Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog tImer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be use to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default 0 6 5 4 3 2 1 0 – – – – – – – ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0 0 0 0 0 0 0 0 Data Byte 13 Bit 7 6 5 4 3 2 1 0 Pin# – – – – – – – – Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default 0 0 0 0 0 0 0 0 Data Byte 14 Bit 7 Pin# – Name Pro_Freq_EN Pin Description Programmable output frequencies enabled 0 = Disabled 1 = Enabled If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default 0 6 5 4 3 2 1 0 Data Byte 15 Bit 7 6 5 4 3 – – – – – – – CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 0 0 0 0 0 0 0 Pin# 1 7 8 11 10 Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input Pin Description Latched FS[4:0] inputs. These bits are Read-only. Power-on Default X X X X X Rev 1.0, November 21, 2006 Page 11 of 18 CY28325-3 Data Byte 15 Bit 2 1 0 Data Byte 16 Bit 7 6 5 4 3 2 1 0 Data Byte 17 Bit 7 6 5 4 3 2 1 0 Pin# – – – – – – – – Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-on Default 0 0 0 0 0 0 0 0 The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Pin# – – – – – – – – Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power-on Default 0 0 0 0 0 0 0 0 Pin# – – – Reserved Vendor Test Mode Vendor Test Mode Name Reserved Reserved. Set = 1 Reserved. Set = 1 Pin Description Power-on Default 0 1 1 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. Table 5. Register Summary . Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = Disabled (default). 1 = Enabled. When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. Rev 1.0, November 21, 2006 Page 12 of 18 CY28325-3 Table 5. Register Summary (continued). Name FS_Override Description When Pro_Freq_EN is cleared or disabled 0 = Select operating frequency by FS input pins (default). 1 = Select operating frequency by SEL bits in SMBus control bytes. When Pro_Freq_EN is set or enabled 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default). 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes. When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]. When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. 0 = Stop and reload Watchdog Timer. 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write). These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 6. The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. CPU_FSEL_N, CPU_FSEL_M ROCV_FREQ_SEL ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] WD_EN WD_TO_STATUS WD_TIMER[4:0] WD_PRE_SCALER RST_EN_WD RST_EN_FC Program the CPU output frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3). “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. Rev 1.0, November 21, 2006 Page 13 of 18 CY28325-3 Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 50 MHz–129 MHz 130 MHz–248 MHz Gear Constants 48.00741 48.00741 Fixed Value for M-Value Register 93 45 Range of N-Value Register for Different CPU Frequency 97 - 255 127 - 245 Absolute Maximum Conditions[2] Parameter Description Condition Maximum functional voltage Maximum functional voltage Relative to V SS Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. 2000 31.03 77.42 V–0 1 Min. –0.5 –0.5 –0.5 –65 0 Max. 5.5 5.5 VDD + 0.5 150 70 150 – Unit V V V °C °C °C V °C/W °C/W VDD, VDDC, 3.3V Supply Voltage VDDA, VDDX VDDQ VIN TS TA TJ ESDHBM ØJC ØJA UL–94 MSL Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Operating Conditions Parameter VDD_REF, VDD_PCI,VDD_AGP, VDD_CPU, VDD_48MHz VDD_CPPU_CS Cin CXTAL CL Description 3.3V Supply Voltages CPU_CS Supply Voltage Input Pin Capacitance XTAL Pin Capacitance Max. Capacitive Load on 24_48MHz, 48 MHz, REF PCI, AGP Reference Frequency, Oscillator Nominal Value – – Min. 3.135 2.375 Max. 3.465 2.625 5 22.5 20 30 14.318 Unit V V pF pF pF f(REF) 14.318 MHz Note: 2. Multiple Sequence: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Rev 1.0, November 21, 2006 Page 14 of 18 CY28325-3 DC Electrical Specifications Parameter VIH VIL VOH VOL IIH IIL IIPUL IOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input HIGH Current Input LOW Current Input LOW Current High-level Output Current Except Crystal Pads 24_48MHz, 48 MHz, REF, AGP PCI 24_48MHz, 48 MHz, REF, AGP PCI 0 < VIN < VDD 0 < VIN < VDD, except inputs with pull-ups 0 < VIN < VDD, inputs with pull-ups CPUT0:1,CPUC0:1 For IOH =6*IRef Configuration REF, 24_48MHz, 48 MHz AGP, PCI IOL Low-level Output Current REF, 24_48MHz, 48 MHz AGP, PCI IDD33 IDD25 IDDPD - Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 IOH = –1 mA IOH = –1 mA IOL = 1 mA IOL = 1 mA Min. Max. Unit 2.4 – 2.4 2.4 – – –5 –5 –50 Type X1, VOH = 0.65V Type X1, VOH = 0.74V Type 3, VOH = 1.00V Type 3, VOH = 3.135V Type 5, VOH = 1.00V Type 5, VOH = 3.135V Type 3, VOL = 1.95V Type 3, VOL = 0.4V Type 5, VOL =1.95 V Type 5, VOL = 0.4V –12.9 – –29 – –33 – 29 – 30 – – – – – 0.8 – – 0.4 0.55 5 5 – – –14.9 – –23 – –33 – 27 – 38 250 75 20 mA mA mA mA V V V V V V A A A mA Power Supply Current Power Supply Current Shutdown Current 3.3 VDD = 3.465V, 2.5 VDD = 2.625V 3.3 VDD = 3.465V AC Electrical Specifications[3] Parameter t1 t1 t1 t1 t1 t2 Output Description Cycle[4] Test Conditions Measured at 1.5V Measured at 1.5V Measured at VCROSS Measured at VCROSS 166MHz Measured at VCROSS @ 200MHz Between 0.8V and 2.0V Min. 40 35 45 45 30 0.5 Max. 60 65 55 55 70 2.2 Unit % % % % % ns 24_48 MHz, 48 Output Duty MHz, REF, PCI APIC, AGP CPUT/C CPUT/C_CS CPUT/C_CS Output Duty Cycle[4] Output Duty Cycle Output Duty Cycle Output Duty Cycle 24_48 MHz, 48 Rising Edge Rate[6] MHz, PCI, PCI_F, REF, AGP APIC Rising Edge Rate[6] 24_48 MHz, 48 Falling Edge Rate MHz, PCI, PCI_F, REF, AGP APIC AGP[0:2] PCI AGP, APIC Falling Edge Rate[7] AGP-AGP Skew PCI-PCI Skew Cycle-Cycle Clock Jitter t2 t3 Between 0.8V and 2.0V Between 2.0V and 0.8V 0.5 0.5 2.3 2.2 ns ns t3 t5 t6 t9 t9 t9 Between 2.0V and 0.8V Measured at 1.5V Measured at 1.5V Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B 0.5 – – – – – 2.3 300 500 500 350 500 ns ps ps ps ps ps 24_48 MHz, 48 Cycle-Cycle Clock Jitter MHz PCI Cycle-Cycle Clock Jitter Rev 1.0, November 21, 2006 Page 15 of 18 CY28325-3 AC Electrical Specifications[3] (continued) Parameter t9 t2 t3 t4 t8 Output REF CPU CPU CPU CPU CPU Voh Vol Vcrossover CPU CPU CPU Description Cycle-Cycle Clock Jitter Rise Time Fall Time CPU-CPU Skew Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage Test Conditions Measured at 1.5V t9 = t9A – t9B Min. – Max. 1000 1.6 1.6 150 300 20 0.85 – 0.43 Unit ps ns ns ps ps % V V V 0.7V CPUT/C, CPU_CS Measured single ended waveform from 0.175 0.175V to 0.525V Measured single ended waveform from 0.175 0.525V to 0.175V Measured at Crossover Measured at Crossover t8 = t8A – t8B With all outputs running Measured with test loads[5, 6] Measured with test loads[6] Measured with test loads[6] Measured with test loads[6] – – – – –0.15 0.28 Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measure at 1.25V. 5. Determined as a fraction of 2*(Trp-Trn)(TRP+Trn) where Trp is a rising edge and Trp is an intersectiong falling edge. 6. The 0.7V test load is RS=33.2ohm, RP = 49.9ohm in test circuit. 7. Characterize with control register, data byte 9, bits 5 and 6 = 1. Rev 1.0, November 21, 2006 Page 16 of 18 CY28325-3 Switching Waveforms (continued) CPU-CPU Clock Skew Host_b Host Host_b Host t4 AGP-AGP Clock Skew AGP AGP t5 PCI-PCI Clock Skew PCI PCI t6 CPU Clock Cycle-Cycle Jitter t8A Host_b Host t8B Cycle-Cycle Clock Jitter t9A t9B CLK Ordering Information Ordering Code CY28325OC-3 CY28325OC-3T CY28325OXC-3 CY28325OXC-3T Package Type 48-pin Shrunk Small Outline Package (SSOP) 48-pin Shrunk Small Outline Package (SSOP) - Tape and Reel 48-pin Shrunk Small Outline Package (SSOP)- Lead Free Operating Range Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C 48-pin Shrunk Small Outline Package (SSOP) - Tape and Reel- Lead Free Commercial, 0°C to 70°C Rev 1.0, November 21, 2006 Page 17 of 18 CY28325-3 Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 18 of 18