CY28341OC-3

CY28341-3 Universal Clock Chip for VIA™P4M/KT/KM400A DDR Systems Features • Supports VIA P4M/KM/KT/266/333/400A chipsets • Supports Intel Pentium 4, Athlon™ processors • Supports two DDR DIMMS • Provides: — Two different programmable CPU clock pairs — Six differential DDR pairs — Three low-skew/-jitter AGP clocks — Seven low-skew/-jitter PCI clocks — One 48M output for USB — One programmable 24M or 48M for SIO • Dial-A-Frequency and Dial-A-dB features • Spread Spectrum for best EMI reduction • Watchdog feature for system recovery • SMBus-compatible for programmability • 56-pin SSOP and TSSOP packages Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 100.9 100.0 133.9 133.3 110.0 145.2 180.0 198.4 200.9 200.0 166.9 166.6 100.0 133.3 200.0 166.6 AGP 67.3 66.7 66.9 66.7 73.3 72.6 72.0 71.7 66.9 66.7 66.8 66.6 66.7 66.7 66.7 66.6 PCI 33.6 33.3 33.5 33.3 36.7 36.3 36.0 35.8 33.5 33.3 33.4 33.3 33.3 33.3 33.3 33.3 Block Diagram XIN XOUT XTAL REF0 VDDR REF(0:1) VDDI CPUCS_T/C FS0 Pin Configuration[1] SELP4_K7# VDDC CPU(0:1)/CPU0D_T/C VDDPCI FS2 PLL1 FS3 FS1 PCI(3:6) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M 48M /2 PD# SDATA SCLK SMBus PLL2 WDEN 24_48M WD SRESET# VDDD FBOUT S2D CONVERT DDRT(0:5) DDRC(0:5) *FS0/REF0 VSSR XIN XOUT VDDAGP AGP0 *SELP4_K7/AGP1 AGP2 VSSAGP **FS1/PCI_F PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 PCI6 VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD#/SRESET# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VTTPWRGD#/REF1 VDDR VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T VSSI FBOUT BUF_IN DDRT0 DDRC0 DDRT1 DDRC1 VDDD VSSD DDRT2 DDRC2 DDRT3 DDRC3 VDDD VSSD DDRT4 DDRC4 DDRT5 DDRC5 CY28341-3 Buf_IN 56 pin SSOP Note: 1. Pins marked with [*] have internal 250 K pull-up resistors. Pins marked with [**] have internal 250 K pull-down resistors. Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 19 www.SpectraLinear.com CY28341-3 Pin Description[2] Pin Number 3 4 1 XIN XOUT FS0/REF0 VDDR 56 VTTPWRGD# VDDR I VDD Pin Name PWR I/O I O Pin Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS0 state is PU latched and this pin becomes REF0, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is 1 x strength.) If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At power-up, VTT_PWRGD# is an input. When this input transitions to a logic low, the FS (3:0) and MULTSEL are latched and all output clocks are enabled. After the first high to low transition on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the device thereafter. When the VTT_PWRGD# feature is not used, please connect this signal to ground through a 10K resistor. If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C). VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes REF1 and is a buffered copy of the signal applied at XIN. DDR Clock Outputs. DDR Clock Outputs. REF1 VDDR 44,42,38, 36,32,30 43,41,37 35,31,29 7 DDRT (0:5) DDRC (0:5) SELP4_K7 / AGP1 VDDD VDDD O O O Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input. I/O When the power supply voltage crosses the input threshold voltage, VDDAGP PU SELP4_K7 state is latched and this pin becomes AGP1 clock output. SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode. VDDPCI Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. I/O When the power supply voltage crosses the input threshold voltage, MULTSEL PU state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x IREFMULTSEL = 1, Ioh is 6 x IREF O 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock Output. See Table 1 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock Output. See Table 1 2.5V CPU Clock Outputs for Chipset. See Table 1. PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1 12 MULTSEL/PCI2 53 CPUT/CPUOD_T VDDC 52 CPUC/CPUOD_C VDDC O O O 48,49 10 CPUCS_T/C FS1/PCI_F VDDI VDDPCI VDDPCI 14,15,17,18 PCI (3:6) Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS1 state is PD latched and this pin becomes PCI_F clock output. Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS3 state is PD latched and this pin becomes 48M, a USB clock output. I/O PCI Clock Output. PD Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS2 state is PD latched and this pin becomes 24_48M, a SIO programmable clock output. O O AGP Clock Output. Is synchronous to CPU clocks. See Table 1. AGP Clock Output. Is synchronous to CPU clocks. See Table 1. (range 200 K to 500 K ). 20 FS3/48M VDD48M 11 21 PCI1 FS2/24_48M VDDPCI VDD48M 6 8 AGP0 AGP2 VDDAGP VDDAGP Note: 2. PU = internal pull-up. PD = internal pull-down. Typically = 250 K Rev 1.0, November 21, 2006 Page 2 of 19 CY28341-3 Pin Description[2] (continued) Pin Number 25 28 Pin Name IREF SDATA PWR I/O I Pin Description Current reference programming input for CPU buffers. A precise resistor is attached to this pin, which is connected to the internal current reference. Serial Data Input. Conforms to the Phillips I2C specification of a Slave I/O Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. I Serial Clock Input. Conforms to the Philips I2C specification. Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0(default), this pin becomes a SRESET# open drain output. See system reset description. I/O If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When PU PD# is asserted low, the device enters power down mode. See power management function. Input to DDR Differential Buffers. 2.5V single-ended SDRAM buffered output of the signal applied at BUF_IN. 3.3V power supply for AGP clocks. 3.3V power supply for CPUT/C clocks. 3.3V power supply for PCI clocks. 3.3V power supply for REF clock. 2.5V power supply for CPUCS_T/C clocks. 3.3V power supply for 48M. 3.3V Common power supply. 2.5V power supply for DDR clocks. Ground for AGP clocks. Ground for PCI clocks. Ground for CPUT/C clocks. Ground for DDR clocks. Ground for 48M clock. Ground for CPUCS_T/C clocks. Ground for REF. Common Ground. 27 26 SCLK PD#/SRESET# 45 46 5 51 16 55 50 22 23 34,40 9 13 54 33,39 19 47 2 24 BUF_IN FBOUT VDDAGP VDDC VDDPCI VDDR VDDI VDD_48M VDD VDDD VSSAGP VSSPCI VSSC VSSD VSS_48M VSSI VSSR VSS Power Management Functions All clocks can be individually enabled or stopped via the two-wire control interface. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stop and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.5 mS. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Rev 1.0, November 21, 2006 Page 3 of 19 CY28341-3 Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave ...................... Data Byte (N–1) –8 bits Acknowledge from slave Data Byte N –8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte N from slave – 8 bits Acknowledge from master Stop Block Read Protocol Description 19 20:27 28 19 20 21:27 Rev 1.0, November 21, 2006 Page 4 of 19 CY28341-3 Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 29 Stop Description Bit 28 29 30:37 38 39 Read = 1 Acknowledge from slave Data byte from slave – 8 bits Acknowledge from master Stop Byte Read Protocol Description Serial Control Registers Byte 0: Frequency Select Register Bit 7 6 5 4 3 @Pup 0 H/W Setting H/W Setting H/W Setting 0 21 10 1 Pin# Name Reserved FS2 FS1 FS0 FS_Override Reserved For Selecting Frequencies in Frequency Selection Table on page 1 For Selecting Frequencies in Frequency Selection Table on page 1 For Selecting Frequencies in Frequency Selection Table on page 1 If this bit is programmed to “1”, it enables WRITE to bits (6:4,1) for selecting the frequency via software (SMBus) If this bit is programmed to a “0” it enable only READ of bits (6:4,1), which reflect the hardware setting of FS(0:3). Reserved, set = 0 For Selecting frequencies in Frequency Selection Table on page 1 Only for reading the hardware setting of the CPU interface mode, status of SELP4_K7# strapping. Description 2 1 0 0 H/W Setting H/W Setting 11 20 7 Reserved FS3 SELP4_K7 Byte 1: CPU Clocks Register Bit 7 6 5 4 3 2 1 @Pup 0 1 1 1 1 1 0 Pin# MODE SSCG SST1 SST0 48,49 CPUCS_T, CPUCS_C 53,52 CPUT/CPUOD_T CPUC/CPUOD_C 53,52 CPUT/C Name Description 0 = Down Spread. 1 = Center Spread. See Table 9 on page 8 1 = Enable (default). 0 = Disable Select spread bandwidth. See Table 9 on page 8 Select spread bandwidth. See Table 9 on page 8 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disable. In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW, CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when PD# asserted LOW, CPUT and CPUC stop in High-Z. Only for reading the hardware setting of the Pin11 MULT0 value. 0 1 11 MULT0 Byte 2: PCI Clock Register Bit 7 6 5 4 3 @Pup 0 1 1 1 1 10 18 17 15 Pin# Name PCI_DRV PCI_F PCI6 PCI5 PCI4 Description PCI clock output drive strength 0 = Low strength, 1 = High strength 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. Rev 1.0, November 21, 2006 Page 5 of 19 CY28341-3 Byte 2: PCI Clock Register (continued) 2 1 0 1 1 1 14 12 11 PCI3 PCI2 PCI1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. Byte 3: AGP/Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 0 0 1 1 1 Pin# 21 20 21 6,7,8 6,7,8 8 7 6 Name 24_48M 48MHz 24_48M DASAG1 DASAG0 AGP2 AGP1 AGP0 Description 0 = pin21 output is 24MHz. Writing a '1' into this register asynchronously changes the frequency at pin21 to 48 MHz. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low Programming these bits allow shifting skew of the AGP(0:2) signals relative to their default value. See Table 5. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low Table 5. Dial-a-Skew DASAG (1:0) 00 01 10 11 AGP(0:2) AGP(0:2) Skew Shift Default –280 ps +280 ps +480 ps Byte 4: Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 1 1 1 1 Pin# 20 21 6,7,8 6,7,8 1 56 1 56 48M 24_48M DARAG1 DARAG0 REF0 REF1 REF0 REF1 Name Description 1 = Low strength, 0 = High strength 1 = Low strength, 0 = High strength Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 6. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = Low strength, 0 = High strength 1 = Low strength, 0 = High strength (K7 Mode only) Table 6. Dial-A-Ratio DARAG (1:0) 00 01 10 11 AGP(0:2) CU/AGP Ratio Frequency Selection Default 2/1 2.5/1 3/1 Byte 5: SDR/DDR Clock Register Bit 7 @Pup 0 Pin# 45 Name BUF_IN threshold voltage FBOUT DDRT/C5 Description DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V 6 5 1 1 46 29,30 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. Rev 1.0, November 21, 2006 Page 6 of 19 CY28341-3 Byte 5: SDR/DDR Clock Register (continued) Bit 4 3 2 1 0 @Pup 1 1 1 1 1 Pin# 31,32 35,36 37,38 41,42 43,44 Name DDRT/C4 DDRT/C3 DDRT/C2 DDRT/C1 DDRT/C0 Description 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. Byte 6: Watchdog Register Bit 7 @Pup 0 Pin# 26 Name SRESET# Description 1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET# signal. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = select frequency of existing H/W setting, 1 = select frequency of the second to last S/W table setting. (the software setting prior to the one that caused a system reboot). For IMI Test - WD-Test, ALWAYS program to '0' This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears the WD time stamps (WD3:0). This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Frequency Revert WDTEST WD Alarm WD3 WD2 WD1 WD0 Table 7. Watchdog Time Stamp WD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds FUNCTION Rev 1.0, November 21, 2006 Page 7 of 19 CY28341-3 Byte 7: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Name Reserved N6, MSB N5 N4 N3 N2 N3 N0, LSB Description Reserved for device function test. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Byte 8: Silicon Signature Register (all bits are read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Pin# Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Revision ID bit [3] Revision ID bit [2] Revision ID bit [1] Revision ID bit [0] Cypress’s Vendor ID bit [3]. Cypress’s Vendor ID bit [2]. Cypress’s Vendor ID bit [1]. Cypress’s Vendor ID bit [0]. Description Byte9: Dial-A-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Name Reserved R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is load from DAF (SMBus) registers. Table 9. Spread Spectrum Table Mode 0 0 0 0 FS(4:0) XXXXX P 96016000 1 1 1 1 SST1 0 0 1 1 0 0 1 1 SST0 0 1 0 1 0 1 0 1 % Spread –1.5% –1.0% –0.7% –0.5% ±0.75% ±0.5% ±0.35% ±0.25% Reserved These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description Dial-A-Frequency Feature SMBus Dial-a-Frequency feature is available in this device via Byte7 and Byte9. P is a PLL constant that depends on the frequency selection prior to accessing the Dial-a-Frequency feature. Table 8. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 7. Rev 1.0, November 21, 2006 Page 8 of 19 CY28341-3 Swing Select Functions Through Hardware MULTSEL 1 Board Target Trace/Term Z 50 Ohm Reference R, IREF = VDD/(3*Rr) Rr = 475 1%, IREF = 2.32mA Output Current IOH = 6* Iref VOH@Z 0.7V@50 Watchdog Self-Recovery Sequence This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang-up due to the frequency change. When the system sends an SMBus command requesting a frequency change through the Dial-a-Frequency Control Registers, it must have previously sent a command to the Watchdog timer to select which time-out stamp the Watchdog must perform, otherwise the System Self-Recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in the Watchdog timer bits (reprogram to 0000) before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. The Watchdog timer will also be triggered if you program the software frequency select bits (FSEL) to a new frequency selection. If the Watchdog times out before the new SMBus reprograms the Watchdog timer bits to (0000), then this device send a low system reset pulse, on SRESET# and changes Watchdog time-out bit to “1”. W AT C H D O G T IM E R P R O G R AM M IN G R E S E T W AT C H D O G T IM E R S et W D T im er B its = 0 C l ear W D A lar m bit = 0 IN IT IAL IZ E W AT C H D O G T IM E R S et F r eq uenc y R ever t B it S et W D T im er B its C H AN G E F R E Q B Y S E T S O F T W AR E F S E L S et S W F r eq _S el bi ts S et F S over r ide bit C H AN G E F R E Q B Y S E T D IAL - A- R AT IO S el ec t a differ ent divider r atio C H AN G E F R E Q B Y S E T D IAL - AF R EQU EN C Y Load M and N R eg i s ter s S et P r o_F r eq _E N = 1 C O U N T D O W N W D T IM E R S end 3m s R es et P ul s e NO W D T im er = 0 C L E AR W D T IM E R S et W D A lar m = 1 F req u en cy R ev ert B it = 0 S et F r eq uenc y to F S _H W _Latc hed F req u en cy R ev ert B it = 1 S et F r eq uenc y to F S _S W S etti ng S R E S E T # = 0 f o r 3 m sec R eset & R ev ert F req u en cy b ack Figure 1. Watchdog Self Recovery Sequence Flowchart Rev 1.0, November 21, 2006 Page 9 of 19 CY28341-3 P4 Processor SELP4_K7# = 1 Power-down Assertion (P4 Mode) When PD# is sampled low by two consecutive rising edges of CPU# clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. Note that Figure 1 shows CPU = 133 MHz. This diagram and description are applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power-down Deassertion (P4 Mode) The power-up latency needs to be less than 3 mS. AMD K7 processor SELP4_K7# = 0 Power-down Assertion (K7 Mode) When the PD# signal is asserted low, all clocks are disabled to a low level in an orderly fashion prior to removing power from the part. When PD# is asserted (forced) low, the device transitions to a shutdown (power down) mode and all power supplies may then be removed. When PD# is sampled low by two consecutive rising edges of CPU clock, then all affected clocks are stopped in a low state as soon as possible. When in power down (and before power is removed), all outputs are synchronously stopped in a low state (see Figure 3 below), all PLL's are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled. PD# C P U T 1 33 M H z C P U C 1 33 M H z P C I 33 M H z A G P 66 M H z U S B 48 M H z R E F 1 4.3 18 M H z D D R T 1 33 M H z D D R C 1 33 M H z Figure 2. Power-down Assertion Timing Waveform (in P4 Mode) < 1 .5 m sec PD# CPUT 133M Hz CPUC 133M Hz PCI 33M Hz AG P 66M Hz USB 48M Hz R E F 1 4 .3 1 8 M H z DDRT 133M Hz DDRC 133M Hz Figure 3. Power-down Deassertion Timing Waveform (in P4 mode) Rev 1.0, November 21, 2006 Page 10 of 19 CY28341-3 PD# CPUOD_T 133MHz CPUCS_T 133MHz CPUOD_C 133MHz CPUCS_C 133MHz P CI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz D DRT 133MHz DDRC 133MHz Figure 4. Power-down Assertion Timing Waveform (In K7 Mode) Power-down Deassertion (K7 Mode) When deasserted PD# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch free operation, no partial clock pulses.