CY28344PVC

CY28344 FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan and CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Brookdale (845) and Brookdale G Pentium® 4 Chipsets • Programmable clock output frequency with less than 1MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW-selected or SW-programmed clock frequency when Watchdog timer time-out • Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte Read/Write and block Read/Write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP CPU ×3 3V66 ×4 PCI ×9 REF ×1 48M ×2 Block Diagram X1 X2 Pin Configuration[1] VDD_REF REF_2X XTAL OSC PLL 1 PLL Ref Freq Divider Network VDD_CPU CPU0:2, CPU0:2#, FS0:4 MULTSEL0 VDD_3V66 3V66_1:3 VDD_3V66 3V66_0/VCH_CLK VTTPWRGD/PD# VDD_PCI PCI_F0:1 PCI0:6 PLL2 VDD_48MHz 48MHz VDD_REF X1 X2 GND_REF ^FS0/PCI_F0 ^FS1/PCI_F1 VDD_PCI GND_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI GND_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 3V66_1 3V66_2 3V66_3 RST# VDD_CORE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF_2X/FS2^ CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU VDD_CPU CPU2 CPU2# MULTSEL0 IREF GND_CPU 48MHz/FS3^ 24_48MHz VDD_48MHz GND_48MHz 3V66_0/VCH_CLK/FS4^ VDD_3V66 GND_3V66 SCLK SDATA VTTPWRGD/PD#* GND_CORE ~ 24_48MHz 2 SSOP-48 Note: 1. Signals marked with “*” and “^,” respectively, have internal pull-up and pull-down resistors. CY28344 SDATA SCLK SMBus Logic RST# Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 21 www.SpectraLinear.com CY28344 Pin Definitions Pin Name X1 Pin No. 2 Pin Type I Pin Description Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock/Frequency Select 2: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Current Multiplier Selection 0: 3.3V input to select the current multiplier for CPU clock outputs. The MULTSEL0 is as follows: MULTSEL0 0 = Ioh is 4 × IREF 1 = Ioh is 6 × IREF CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. 66MHz Clock Outputs: 3.3V 66-MHz clock. 66MHz Clock Output/Frequency Select 4: 3.3V 66-MHz or 48-MHz clock output. The selection is determined by the control byte register. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 0/Frequency Select 0: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 1/Frequency Select 1: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI Clock Output 0 to 6: 3.3V PCI clock outputs. X2 REF_2X/FS2 3 48 O I/O MULTSEL0 38 I 47, 44, 40, 46, 43,39 3V66_1:3 20, 21, 22 3V66_0/VCH_CLK/F 31 S4 CPU0:2, CPU0:2# O O I/O PCI_F0/FS0 5 I/O PCI_F1/FS1 6 I/O PCI0:6 48MHz/FS3 9, 10, 11, 12, 15, 16, 17 35 O I/O 24_48MHz SCLK SDATA RST# 34 28 27 23 IREF VTT_PWRGD/PD# 37 26 VDD_REF, VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU VDD_48MHz GND_PCI, GND_48MHz, GND_3V66, GND_CPU, GND_REF, 1, 7, 13, 18, 30, 33, 41, 45 I/O I I/O O (opendrain) I Current Reference for CPU output: A precision resistor is attached to this pin, which is connected to the internal current reference. I Powergood from Voltage Regulator Module (VRM)/PD#: 3.3V LVTTL input. VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and MULTSEL0 inputs are valid and OK to be sampled (Active HIGH). P 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 48MHz Output/Frequency Select 3: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. 24 or 48MHz Output: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output. SMBus Clock Input: Clock pin for serial interface. SMBus Data Input: Data pin for serial interface. System Reset Output: Open-drain system reset output. 33 4, 8, 14, 19, 29, 32, 36, 42 P G 3.3V Power Connection: 48MHz output buffers. Connect to 3.3V. Ground Connection: Connect all ground pins to the common system ground plane. Rev 1.0, November 21, 2006 Page 2 of 21 CY28344 Pin Definitions (continued) Pin Name VDD_CORE GND_CORE Pin No. 24 25 Pin Type P G Pin Description 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. Analog Ground Connection: Ground for core logic, PLL circuitry. Swing Select Functions (SW control) SW_MULTSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SW_MULTSEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 50 Ohm 60 Ohm 50 Ohm 60 Ohm 50 Ohm 60 Ohm 50 Ohm 60 Ohm 50 Ohm 60 Ohm 50 Ohm 60 Ohm 50 Ohm 60 Ohm 50 Ohm 60 Ohm Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Output Current IOH = 4*Iref IOH = 4*Iref IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 7*Iref IOH = 7*Iref IOH = 4*Iref IOH = 4*Iref IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 7*Iref IOH = 7*Iref VOH @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 60 0.47V @ 50 0.56V @ 60 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60 Swing Select Functions (HW control) MULTSEL0 0 0 1 1 Board Target Trace/Term Z 50 Ohm 60 Ohm 50 Ohm 60 Ohm Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Output Current IOH = 4*Iref IOH = 4*Iref IOH = 6*Iref IOH = 6*Iref VOH @ Z 1.0V @ 50 1.2V @ 60 1.5V @ 50 1.8V @ 60 Rev 1.0, November 21, 2006 Page 3 of 21 CY28344 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to it’s default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte Write, byte Read, block Write and block Read operation from the controller. For block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte Write and byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block Write and block Read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte Write and byte Read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 6:0 0 = Block Read or block Write operation 1 = Byte Read or byte Write operation Byte offset for byte Read or byte Write operation. For block Read or block Write operations, these bits should be “0000000” Descriptions Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave address – 7 bit Write Acknowledge from slave Command Code – 8 bit “00000000” stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave address – 7 bit Write Acknowledge from slave Command Code – 8 bit “00000000” stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/acknowledge Data byte N from slave – 8 bits Not acknowledge Stop Block Read Protocol Description Rev 1.0, November 21, 2006 Page 4 of 21 CY28344 Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bit Write Acknowledge from slave Command Code – 8 bit “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bit Write Acknowledge from slave Command Code – 8 bit “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Data byte from slave – 8 bits Not acknowledge Stop Byte Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Data Byte Configuration Map Data Byte 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------SEL3 SEL2 SEL1 SEL0 FS_Override SEL4 Spread Spectrum Enable Reserved 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings SW Frequency selection bits. See Table 4. 0 = OFF; 1 = Enabled Reserved Name Description SW Frequency selection bits. See Table 4. Power On Default 0 0 0 0 0 0 0 0 Data Byte 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 40, 39 44, 43 47, 46 -----Name CPU2, CPU2# CPU1, CPU1# CPU0, CPU0# Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input (Active/Inactive) (Active/Inactive) (Active/Inactive) Latched FS[4:0] inputs. These bits are Read-only. Description Power On Default 1 1 1 X X X X X Rev 1.0, November 21, 2006 Page 5 of 21 CY28344 Data Byte 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 4 Bit Bit 7 Pin# -Name MULTSEL_Override Pin Description This bit control the selection of IREF multiple. 0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins 1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6]. IREF multiplier 00 = Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF (Active/Inactive) Drive 0 = Normal, 1 = HIGH (Active/Inactive) (Active/Inactive) (Active/Inactive) Power On Default 0 Pin# 34 35 --31 31 6 5 24_48MHz 48MHz Reserved Reserved 3V66_0/VCH_CLK 3V66_0/VCH_CLK PCI_F1 PCI_F0 Name (Active/Inactive) (Active/Inactive) Reserved Reserved 0 = 66 MHz; 1 = 48 MHz (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description Power On Default 1 1 0 0 0 1 1 1 Pin# -17 16 15 12 11 10 9 Reserved PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description Power On Default 0 1 1 1 1 1 1 1 Bit 6 Bit 5 --- SW_MULTSEL1 SW_MULTSEL0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 48 -22 21 20 REF_2X REF_DRV 3V66_3 3V66_2 3V66_1 1 0 1 1 1 Rev 1.0, November 21, 2006 Page 6 of 21 CY28344 Data Byte 5 Bit Bit 7 Bit 6 Pin# --Name Spread Option 1 Spread Option 0 “00” = ± 0.25% “01” = – 0.5% “10” = ±0.5% “11” = ±0.38% Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -----34 Reserved Reserved Reserved Reserved Reserved 24_ 48MHZ Reserved Reserved Reserved Reserved Reserved 0 = 24 MHz 1 = 48 MHz 0 0 0 0 0 1 Pin Description Power On Default 0 0 Data Byte 6 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 8 Bit Bit 7 Bit 6 Pin# --Reserved Reserved Name Reserved Reserved Pin Description Power On Default 0 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power On Default 0 0 0 0 0 0 0 0 Pin# Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Vendor ID. This bit is Read-only. Bit[2] of Cypress Vendor ID. This bit is Read-only. Bit[1] of Cypress Vendor ID. This bit is Read-only. Bit[0] of Cypress Vendor ID. This bit is Read-only. Pin Description Power On Default 0 0 0 0 1 0 0 0 Rev 1.0, November 21, 2006 Page 7 of 21 CY28344 Data Byte 8 (continued) Bit Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# ------Name WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 WD_PRE_SCALER Pin Description These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support values from 150 ms – 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 – 80 seconds. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 0 = 150 ms 1 = 2.5 sec Power On Default 1 1 1 1 1 0 Data Byte 9 Bit Bit 7 Pin# -Name 48MHz_DRV Pin Description 48MHz and 24_48MHz clock output drive strength 0 = Normal 1 = High Drive PCI clock output drive strength 0 = Normal 1 = High Drive 3V66 clock output drive strength 0 = Normal 1 = High Drive This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: CY28344 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28344 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28344 from its recovery frequency mode by clearing the WD_EN bit. Reserved Power On Default 0 Bit 6 -- PCI_DRV 0 Bit 5 -- 3V66_DRV 0 Bit 4 -- RST_EN_WD 0 Bit 3 -- RST_EN_FC 0 Bit 2 -- WD_TO_STATUS 0 Bit 1 -- WD_EN 0 Bit 0 -- Reserved 0 Rev 1.0, November 21, 2006 Page 8 of 21 CY28344 Data Byte 10 Bit Bit 7 Bit 6 Bit 5 Pin# ---Name CPU_Skew2 CPU_Skew1 CPU_Skew0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Reserved PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps 3V66 skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Pin Description Power On Default 0 0 0 Bit 4 Bit 3 Bit 2 ---- Reserved PCI_Skew1 PCI_Skew0 0 0 0 Bit 1 Bit 0 --- 3V66_Skew1 3V66_Skew0 0 0 Data Byte 11 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 12 Bit Bit 7 Pin# -Name ROCV_FREQ_SEL Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] Power On Default 0 Pin# --------Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power On Default 0 0 0 0 0 0 0 0 Rev 1.0, November 21, 2006 Page 9 of 21 CY28344 Data Byte 12 (continued) Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 13 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 14 Bit Bit 7 Pin# -Name Pro_Freq_EN Pin Description Programmable output frequencies enabled 0 = disabled 1 = enabled If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power On Default 0 Pin# --------Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power On Default 0 0 0 0 0 0 0 0 Pin# -------Name ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0 Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs. The setting of FS_Override bit determine the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power On Default 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 15 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -------- CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 0 0 0 0 0 0 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power On Default 0 0 0 0 0 0 1 1 Vendor Test Mode Vendor Test Mode Reserved. Write with “1” Reserved. Write with “1” Rev 1.0, November 21, 2006 Page 10 of 21 CY28344 Data Byte 16 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 17 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power On Default 0 0 0 0 0 0 0 0 Pin# --------Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Power On Default 0 0 0 0 0 0 0 0 Rev 1.0, November 21, 2006 Page 11 of 21 CY28344 Table 4. Frequency Selection Table Input Conditions FS4 SEL4 Bit[2] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 Bit[7] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 Bit[6] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 Bit[5] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 Bit[4] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 100.90 100.00 103.00 105.00 107.00 109.00 111.00 114.00 117.00 120.00 127.00 130.00 133.33 170.00 180.00 190.00 133.90 133.33 120.00 125.00 134.90 137.00 139.00 141.00 143.00 145.00 150.00 155.00 160.00 170.00 66.67 200.00 3V66 67.27 66.67 68.67 70.00 71.33 72.67 74.00 76.00 78.00 80.00 84.67 86.67 88.89 56.67 60.00 63.33 66.95 66.67 60.00 62.50 67.45 68.50 69.50 70.50 71.50 72.50 75.00 77.50 80.00 85.00 66.67 66.67 PCI 33.63 33.33 34.33 35.00 35.67 36.33 37.00 38.00 39.00 40.00 42.33 43.33 44.44 28.33 30.00 31.67 33.48 33.33 30.00 31.25 33.73 34.25 34.75 35.25 35.75 36.25 37.50 38.75 40.00 42.50 33.34 33.33 Output Frequency PLL Gear Constants (G) 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 Rev 1.0, November 21, 2006 Page 12 of 21 CY28344 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 – 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. Table 5. Register Summary Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = disabled (default) 1 = enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. FS_Override CPU_FSEL_N, CPU_FSEL_M ROCV_FREQ_SEL ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] WD_EN WD_TO_STATUS Rev 1.0, November 21, 2006 Page 13 of 21 CY28344 Table 5. Register Summary (continued) Name WD_TIMER[4:0] Description These bits store the time-out value of the Watchdog timer. The scale of the timer is determined by the prescaler. The timer can support a value of 150 ms – 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec – 80 sec. When the Watchdog timer reaches “0,” it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N+3) and (M+3) needs to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example uses a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. WD_PRE_SCALER RST_EN_WD RST_EN_FC Program the CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3). “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 50 MHz – 129 MHz 130 MHz – 248 MHz Gear Constants 48.00741 48.00741 Fixed Value for M-Value Register 93 45 Range of N-Value Register for Different CPU Frequency 97 – 255 127 – 245 Rev 1.0, November 21, 2006 Page 14 of 21 CY28344 Maximum Ratings[2] (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Input Voltage.............................................. –0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ....–65 C to +150 C Max. Soldering Temperature (10 sec) ....................... +260 C Junction Temperature................................................ +150 C Package Power Dissipation............................................... 1 Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ > 2000V Operating Conditions Over which Electrical Parameters are Guaranteed Parameter VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_48 MHz, VDD_CPU, VDD_48 MHz TA Cin CXTAL CL Description 3.3V Supply Voltages 48 MHz Supply Voltage Operating Temperature, Ambient Input Pin Capacitance XTAL Pin Capacitance Max. Capacitive Load on 48 MHz, REF PCICLK, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.85 0 Max. 3.465 3.465 70 5 22.5 20 30 14.318 MHz Unit V V C pF pF pF f(REF) Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads 48 MHz, REF, 3V66 PCI 48 MHz, REF, 3V66 PCI 0 < VIN < VDD 0 < VIN < VDD CPU For IOH = 6*IRef Configuration REF, 48 MHz 3V66, PCI IOL Low-level Output Current REF, 48 MHz 3V66, PCI, IOZ IDD3 IDDPD3 Output Leakage Current 3.3V Shutdown Current Three-state VDD_CORE/VDD3.3 = 3.465V Type X1, VOH = 0.65V Type X1, VOH = 0.74V Type 3, VOH = 1.00V Type 3, VOH = 3.135V Type 5, VOH = 1.00V Type 5, VOH = 3.135V Type 3, VOL = 1.95V Type 3, VOL = 0.4V Type 5, VOL =1.95 V Type 5, VOL = 0.4V 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 30 38 10 250 20 mA mA mA 29 27 –33 –33 mA –29 –23 IOH = –1 mA IOH = –1 mA IOL = 1 mA IOL = 1 mA –5 –5 12.9 14.9 2.4 2.4 0.4 0.55 5 5 Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V V V V mA mA mA Note: 2. The voltage on any input or any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Rev 1.0, November 21, 2006 Page 15 of 21 CY28344 - Switching Characteristics[3] Over the Operating Range, PCI,3V66 Clock Outputs.(Lump CapacitanceTest Load = 20 pF) Parameter t1 t3 t3 t5 t5 t6 t7 t9 t9 t9 t9 t2 t3 t4 t8 Voh Vol Vcrossover t2 t3 t4 t8 All USB, REF, DOT PCI,3V66 3V66[0:1] 66BUFF[0:2] PCI 3V66,PCI 3V66 USB, DOT PCI REF CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU Voh Vol Vcrossover CPU CPU CPU Output Description Output Duty Cycle[4] Falling Edge Rate Falling Edge Rate 3V66-3V66 Skew 66BUFF-66BUFF Skew PCI-PCI Skew 3V66-PCI Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter RiseTime Fall Time CPU-CPU Skew Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage RiseTime Fall Time CPU-CPU Skew Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage Test Conditions Measured at 1.5V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.5V Measured at 1.5V Measured at 1.5V 3V66 leads. Measured at 1.5V Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured differential waveform from –0.35V to +0.35V Measured differential waveform from –0.35V to +0.35V Measured at Crossover Measured at Crossover t8 = t8A – t8B Measured with test Measured with test loads[5] loads[5] 0.92 -0.2 0.51 175 175 175 175 1.5 Min. 45 0.5 1.0 Max. 55 2.0 4.0 500 175 500 3.5 250 350 500 1000 467 467 150 150 325 1.45 0.35 0.76 700 700 150 150 20 0.85 -0.15 0.28 0.43 Unit % ps V/ns ps ps ps ns ps ps ps ps ps ps ps ps mV V V V ps ps ps ps % V V V CPU 1.0V Switching Characteristics Measured with test loads[5] Measured with test loads[5] Measured single ended waveform from 0.175V to 0.525V Measured single ended waveform from 0.175V to 0.525V Measured at Crossover Measured at Crossover t8 = t8A – t8B With all outputs running Measured with test loads[3,4] Measured with test loads[4] CPU 0.7V Switching Characteristics Measured with test loads[4] Measured with test loads[4] Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 5. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge. 6. The 0.7V test load is Rs = 33.2 ohm, Rp = 49.9 ohm in test circuit. 7. The 1.0V test load is shown on test circuit page. Rev 1.0, November 21, 2006 Page 16 of 21 CY28344 Switching Waveforms Duty Cycle Timing (Single-Ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD 0V t2 t3 OUTPUT CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 Rev 1.0, November 21, 2006 Page 17 of 21 CY28344 Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t6 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A Host_b Host t8B Cycle-Cycle Clock Jitter t9A t9B CLK Rev 1.0, November 21, 2006 Page 18 of 21 CY28344 Layout Example +3.3V Supply FB VDDQ3 0.005 F 10 F C2 G G G C1 G 1 2 3 4 5 6 7 8 9 10 V G G G G V G G G G 11 12 13 14 15 16 17 18 19 20 21 22 23 24 V G V G Core V 48 47 G 46 V 45 44 G 43 42 V 41 G 40 39 38 37 G 36 35 G 34 *Option A 33 G 32 G 31 V 30 29 G 28 27 26 G 25 G G G FB = Dale ILB1206 – 300 or 2TDKACB2012L – 120 or 2 Murata BLM21B601S Ceramic Caps C1 = 10 – 22 F C2 = 0.005 F C5 = 0.1 F C6 = 10 F G = VIA to GND plane layer V = VIA to respective supply plane layer Note. Each supply plane or strip should have a ferrite bead and capacitors. * If on-board video uses 48 MHz or Dot clock uses Option B All bypass caps on VDD pin = 0.1 uF Low ESR CY28344 VDDQ3 *Option B C5 G G C6 G Rev 1.0, November 21, 2006 Page 19 of 21 CY28344 Test Circuit VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 0.7V Test Load 4, 8, 14, 19, 25, 29, 32, 36, 42 7, 13, 18, 24, 30, 33, 41, 45 Rp Rs CPU OUTPUTS PCI,3V66 Outputs 2pF Test Node 20 pF Ref,USB Outputs Test Nodes Rs Rp 2pF Test Node 30 pF Note: Each supply pin must have an individual decoupling capacitor. Note: All capacitors must be placed as close to the pins as is physically possible. 0.7V amplitude: RS = 33 ohm, RP = 50 ohm VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 4, 8, 14, 19, 25, 29, 32, 36, 42 7, 13, 18, 24, 30, 33, 41, 45 1.0V Test Load 33 2pF Test Node 20 pF Ref,USB Outputs CPU OUTPUTS 475 33 Test Nodes 2pF Test Node 30 pF PCI,3V66 Outputs 1.0V Amplitude 63.4 63.4 Rev 1.0, November 21, 2006 Page 20 of 21 CY28344 Ordering Information Ordering Code CY28344PVC Package Type 48-pin Small Shrunk Outline Package (SSOP) Operating Range Commercial Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 51-85061-B While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 21 of 21