CY28354OXC-400

CY28354-400 210 MHz 24 Output Buffer for 4-DDR DIMMS for VIA Chipsets Support Features • Supports VIA PRO 266, KT266 and P4x266 • Dual 1- to 12-output buffer/driver • Supports up to four DDR DIMMs • Low-skew outputs (< 75 ps) • Supports 266-MHz, 333-MHz and 400-MHz DDR SDRAM • SMBus Read and Write support • Space-saving 48-pin SSOP package Functional Description The CY28354-400 is a 2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 24 outputs to support four unbuffered DDR DIMMS. The CY28354-400 can be used in conjunction with CY28326 similar clock synthesizer for the PTT880 and KTT880 chipsets. The CY28354-400 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled. Block Diagram BUF_INA FB_OUTA DDRAT0 DDRAC0 DDRAT1 DDRAC1 DDRAT2 DDRAC2 DDRAT3 DDRAC3 DDRAT4 DDRAC4 DDRAT5 DDRAC5 DDRBT0 DDRBC0 DDRBT1 DDRBC1 DDRBT2 DDRBC2 DDRBT3 DDRBC3 DDRBT4 DDRBC4 DDRBT5 DDRBC5 FB_OUTB Pin Configuration SSOP Top View VDD2.5 GND FB_OUTB BUFF_INB DDRBT0 DDRBC0 DDRBT1 DDRBC1 GND VDD2.5 DDRAT0 DDRAC0 DDRAT1 DDRAC1 GND VDD2.5 FB_OUTA BUF_INA DDRAT2 DDRAC2 DDRAT3 DDRAC3 VDD2.5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ADDR_SEL SDATA SMBus Decoding SCLOCK I2C_CS VDD2.5 GND ADDR_SEL I2C_CS DDRBT2 DDRBC2 DDRBT3 DDRBC3 GND VDD2.5 DDRAT4 DDRAC4 DDRAT5 DDRAC5 GND VDD2.5 DDRBT4 DDRBC4 DDRBT5 DDRBC5 VDD2.5 GND SDATA SCLK BUFF_INB Rev 1.0, November 22, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 8 www.SpectraLinear.com CY28354-400 Pin Description Pin 11, 13, 19, 21, 38, 36, 5, 7, 44, 42, 32, 30 12, 14, 20, 22, 37, 35, 6, 8, 43, 41, 31, 29 18, 4 17, 3 45 46 25 26 Name DDRA[0:5]T DDRB[0:5]T PWR VDD2.5 I/O O O I PD O I PD I PD I PU I/O PU Description Clock outputs. These outputs provide copies of BUF_INA and BUF_INB, respectively. Clock outputs. These outputs provide complementary copies of BUF_INA and BUF_INB, respectively. Reference input from chipset. 2.5V input. Internal pull-down Feedback clock for chipset. CS for I2C allows for multiple devices to be connected with the same I2C address. Internal pull-down. See Table 1. Selects I2C Address D2/DC. Internal Pull-down SMBus clock input. Internal Pull-up SMBus data input. Internal Pull-up 2.5V voltage supply Ground DDRA[0:5]C VDD2.5 DDRB[0:5]C BUF_INA, BUF_INB FB_OUTA FB_OUTB I2C_CS ADDR_SEL SCLK SDATA VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 1, 10, 16, 23, 28, 33, 39, 48 VDD2.5 2, 9, 15, 24, 27, 34, 40, 47 GND Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 1. Command Code Definition Bit 7 (6:5) (4:0) 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation 01 to address chip when I2C_CS = 0 10 to address chip when I2C_CS = 1 Data Protocol The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The Block Write and Block Read protocol is outlined in Table 2.The slave receiver address is D2/DC depending on the state of the ADDRSEL pin. Description Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '00000' Rev 1.0, November 22, 2006 Page 2 of 8 CY28354-400 Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count from master – 8 bits Acknowledge from slave Data byte 0 from master – 8 bits Acknowledge from slave Data byte 1 from master – 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data Byte N – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte 0 from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop Block Read Protocol Description Serial Configuration Map • The Serial bits will be read by the clock driver in the following order. Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0” • SMBus Address for the CY28354 is as follows. A6 SEL ADDR = 1 SEL ADDR = 0 1 1 A5 1 1 A4 0 0 A3 1 1 A2 0 1 A1 0 1 A0 R/W 1 0 — — Rev 1.0, November 22, 2006 Page 3 of 8 CY28354-400 Byte 22: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default (Hi-z) = Active Bit Bit 7 Bit 6 @Pup 0 0 Pin # Input Threshold Control 00: Normal (1.25V) 01: 1.20V 10: 1.15V 11: 1.10V 17 3 30, 29 32, 31 42, 41 44, 43 FBOUTA Control, 0 = Enable, 1 = Disable FBOUTB Control, 0 = Enable, 1 = Disable DDRBT5, DDRBC5 DDRBT4, DDRBC4 DDRBT3, DDRBC3 DDRBT2, DDRBC2 Description Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 1 1 1 Byte 23: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 1 1 1 1 1 1 1 1 7, 8 5, 6 36, 35 38, 37 21, 22 19, 20 13, 14 11, 12 Pin # DDRBT1, DDRBC1 DDRBT0, DDRBC0 DDRAT5, DDRAC5 DDRAT4, DDRAC4 DDRAT3, DDRAC3 DDRAT2, DDRAC2 DDRAT1, DDRAC1 DDRAT0, DDRAC0 Description Rev 1.0, November 22, 2006 Page 4 of 8 CY28354-400 Absolute Maximum Conditions[1] Parameter VDD Vin Vout Ts Ta ØJC ØJA ESDh Description Supply Voltage to Ground Potential DC Input Voltage (except BUFF_IN) Output Voltage Temperature, Storage Temperature, Operating Ambient Dissipation, Junction to Case (Mil-Spec 883E Method 1012.1) Dissipation, Junction to Ambient (JEDEC (JESD 51) ESD Protection (Human Body Model) – Min. –0.5 –0.3 1.1 –65 0 36.39 77.99 2000 Max. 4.6 VDD+0.3 VDD–0.4 +150 85 Unit V V V °C °C °C/W °C/W V DC Electrical Specifications Parameter VDD2.5 COUT CIN Supply Voltage Output Capacitance Input Capacitance Description Min. 2.3 – – Typ. – 6 5 Max. 2.7 – – Unit V pF pF AC Electrical Specifications Parameter VIL VIH IOH IOL VOL VOH IDD IDD IDDPD VOUT VOC INDC Description Input LOW Voltage Input HIGH Voltage Output HIGH Current Output LOW Current Output LOW Voltage[2] Output HIGH Voltage[2] Supply Current[2] Supply Current Supply Current Output Voltage Swing Output Crossing Voltage Input Clock Duty Cycle VDD = 2.375V, VOUT = 1V VDD = 2.375V, VOUT = 1.2V IOL = 12 mA, VDD = 2.375V IOH = –12 mA, VDD = 2.375V Unloaded outputs, 133 MHz Loaded outputs, 133 MHz All outputs off See Test Circuity. See Figure 1 Conditions For all pins except SMBus Min. 0.3 1.7 – – – 1.7 – – – 0.7 VDD/2–0.3 40 Typ. – – – – – – – – – – VDD/2 – Max. 0.7 VDD + 0.3 –12 12 0.5 – 400 500 2 VDD + 0.6 VDD/2+0.3 60 Unit V V mA mA V V mA mA mA V V % Switching Characteristics[3] Parameter – – t3d t4d t5 t6 Name Operating Frequency Duty Cycle[2, 4] = t2 t1 Measured differentially at VCROSS Measured single ended at 20% to 80% of VDIF Measured single ended at 80% to 20% of VDIF DDR Rising Edge Rate[2] DDR Falling Edge Rate[2] Test Conditions Min. 60 INDC –2% 1.0 1.0 – – – 2.0 2.0 – – Typ. Max. 210 INDC +2% 5.0 5.0 75 6 Unit MHz % V/ns V/ns ps ns Output to Output Skew for All outputs equally loaded. DDR[2] See Figure 1. Input to Output Propagation At output load of 15 pFn delay Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3. All parameters specified with loaded outputs. 4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns. Rev 1.0, November 22, 2006 Page 5 of 8 CY28354-400 Switching Waveforms V OH V V OL D IF V CROSS V SS Duty Cycle Timing t1 t2 Output-Output Skew OUTPUT OUTPUT t5 Figure 1 shows the differential clock directly terminated by a 120 VCC VCC resistor. Device Under Test Out ) ) 60 VTR RT =120 Out 60 VCP Receiver Figure 1. Differential Signal Using Direct Termination Resistor Rev 1.0, November 22, 2006 Page 6 of 8 CY28354-400 Layout Example for DDR 2.5V FB 10 mF 0.005 mF VDDQ2 C3 G C4 G G G G G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 V G G V G G V G G V G 48 47 46 45 44 43 42 41 G 40 V 39 G 38 37 36 35 G 34 V 33 G 32 31 30 29 V 28 G 27 26 G 25 V G G FB = Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB 2012L-120 C4 = 0.005 F Ceramic Caps C3 = 10–22 F G = VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic CY28354-400 G G G Ordering Information Ordering Code Lead Free CY28354OXC–400 CY28354OXC–400T 48-pin SSOP 48-pin SSOP – Tape and Reel Commercial, 0°C to 85 °C Commercial, 0°C to 85 °C Package Type Operating Range Rev 1.0, November 22, 2006 Page 7 of 8 CY28354-400 Package Drawing and Dimension 48-Lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 22, 2006 Page 8 of 8