CY28372

CY28372 SiS 746 AMD Athlon™/AMD Duron™ Clock Synthesizer Features • Supports AMD Athlon /Duron • 3.3V and 2.5V power supply • Eight copies of PCI clocks • One 48-MHz USB clock • Two copies of ZCLK clocks • One 48 MHz/24 MHz programmable SIO clock CPU x2 ZCLK x2 REF x3 PCI x8 AGP x2 IOAPIC x2 48M x1 24_48M x1 • One differential CPU clock (opendrain) CPU • One singled-ended CPU clock (opendrain) • SMBus support with readback capabilities • Spread Spectrum electromagnetic interference (EMI) reduction • 48-pin SSOP package Block Diagram XIN XOUT Pin Configuration VDD_REF REF0:2 XTAL OSC PLL Ref Freq Divider Network VDD_CPU CPUT1 CPUT0, CPUC0 VDD_Z ZCLK0:1 PLL 1 **FS0:3 CPU_STP# VDD_APIC APIC0:1 VDD_PCI PCIF0:1 2 PCI0:5 PCI_STP# Fract. Aligner VDD_AGP AGP0:1 PLL2 PD# VDD_48 48 MHz 24_48MHz 2 VDD_REF **FS0/REF0 **FS1/REF1 REF2 GND_REF XIN XOUT GND_Z ZCLK0 ZCLK1 VDD_Z *PCI_STP# VDD_PCI **FS2/PCIF0 *FS3/PCIF1 PCI0 PCI1 GND_PCI VDD_PCI PCI2 PCI3 PCI4 PCI5 GND_PCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_APIC IOAPIC1 IOAPIC0 GND_APIC CPU_STP#* CPUT1 VDD_CPU GND_CPU CPUT0 CPUC0 VDD_CPU GNDA VDDA SCLK SDATA PD#* GND_AGP AGP0 AGP1 VDD_AGP VDD_48 48MHZ 24_48MHZ GND_48 ~ SDATA SCLK I2C Logic SSOP-48 * : Internal Pull-up 150k ** : Internal Pull-down 150k CY28372 Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 17 www.SpectraLinear.com CY28372 Pin Description Pin #. 6 Name XIN Type I Description Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection. Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock. 14.31818 reference outputs. Reference Clock. 14.31818 reference outputs. Frequency Select. Sampled upon power-on to determine device operating frequency. Free-running PCI. Independent of PCI_STP#. Frequency Select. Sampled upon power-on to determine device operating frequency. PCI Clock. PCI Stop. Stops all PCI clocks Differential CPU Outputs. “True” Clock of Differential CPU Outputs. For chipset host bus CPU Stop. Stops all CPU clocks MuTIOL Clock Outputs. IOAPIC. 2.5 V clock outputs 48 MHz Clock. USB clock outputs 24 MHz or 48 MHz Clock. Selectable SIO clock outputs. Default output frequency is 24 MHz, but can be configured for 48 MHz through I2C. AGP Clock. I2C Data. 5v tolerant I2C Clock.5v tolerant Power-down Control. Turns off all clock outputs and shuts down device 3.3V Analog Power/Ground. Power supply for core logic, PLL circuitry 3.3V Power and Ground. Power supply for respective output buffers. 7 4 2, 3 14, 15 16, 17, 20, 21, 22, 23 12 40 39 43 44 9, 10 46, 47 27 26 31, 30 34 35 33 36 37 1, 5, 8, 11, 13, 18, 19, 24, 25, 28, 29, 32 XOUT REF2 REF[0:1]/ FS[0:1] PCIF[0:1]/ FS[2:3] PCI [0:5] PCI_STP# CPUT0 CPUC0 CPUT1 CPU_STP# ZCLK[0:1] IOAPIC[0:1] 48MHz 24_48MHz AGP[0:1] SDATA SCLK PD# VDDA GNDA VDD_REF, GND_REF, GND_Z, VDD_Z, VDD_PCI, GND_PCI, GND_48, VDD_48, VDD_AGP, GND_AGP VDD_CPU, GND_CPU, VDD_APIC, GND_APIC O O O I O I O I O O I O O O O O I/O I I PWR PWR PWR 38, 41, 42 48, 45 PWR 2.5V Power and Ground. Power supply for respective output buffers. Rev 1.0, November 20, 2006 Page 2 of 17 CY28372 Table 1. Frequency Selection Table Input Conditions I2C Option (byte 4, bit 2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (default) FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU (MHz) 133.3 133.3 133.3 133.3 133.3 133.3 133.3 133.3 100.0 100.0 100.0 100.0 100.0 100.0 111.0 111.0 114.5 120.0 133.3 133.3 133.3 145.7 150.0 166.6 111.1 137.4 144.9 150.0 155.1 166.6 180.1 200.0 Output Frequency ZCLK (MHz) 66.7 66.7 100.0 100.0 133.3 133.3 166.6 166.6 66.7 66.7 100.0 100.0 133.3 133.3 166.5 166.5 95.4 100.0 83.3 111.1 133.3 116.6 100.0 111.1 133.3 137.4 144.9 150.0 124.1 133.3 135.1 133.3 AGP (MHz) 66.7 50.0 66.7 50.0 66.7 50.0 66.7 55.5 66.7 50.0 66.7 50.0 66.7 50.0 66.6 55.5 63.6 66.7 66.7 74.1 83.3 64.8 66.7 66.7 66.7 68.7 64.4 66.7 68.9 66.7 67.6 66.7 PCI (MHz) 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 31.8 33.3 33.3 33.3 33.3 32.4 33.3 33.3 33.3 34.4 32.2 33.3 34.5 33.3 33.8 33.3 VCO Freq. (MHz) 400.0 400.0 400.0 400.0 400.0 400.0 666.5 666.5 400.0 400.0 400.0 400.0 400.0 400.0 666.1 666.1 572.5 600.0 666.5 666.5 666.5 582.8 600.0 666.5 666.5 549.6 579.5 600.0 620.3 666.5 540.4 400.0 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. Rev 1.0, November 20, 2006 Page 3 of 17 CY28372 The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave ...................... Data Byte (N–1) –8 bits Acknowledge from slave Data Byte N –8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop Block Read Protocol Description 19 20:27 19 20 Rev 1.0, November 20, 2006 Page 4 of 17 CY28372 Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 28 29 Stop Description Acknowledge from slave Bit 21:27 28 29 30:37 38 39 Read = 1 Acknowledge from slave Data byte from slave – 8 bits Not Acknowledge Stop Byte Read Protocol Description Slave address – 7 bits Device Configuration Map Data Bytes 0 to 3: Reserved for ZDB Registers Byte 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 @Pup 1 0 0 0 Name Frequency Select Register (FS3) Frequency Select Register (FS2) Frequency Select Register (FS1) Frequency Select Register (FS0) [7..4] Bit2 = 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit2 = 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 114.5 120.0 133.3 133.3 133.3 145.7 150.0 166.6 111.1 137.4 144.9 150.0 155.1 166.6 180.1 200.0 95.4 100.0 83.3 111.1 133.3 116.6 100.0 111.1 133.3 137.4 144.9 150.0 124.1 133.3 135.1 133.3 63.631.8 66.733.3 66.733.3 74.133.3 83.333.3 64.832.4 66.733.3 66.733.3 66.733.3 68.734.4 64.432.2 66.733.3 68.934.5 66.733.3 67.633.8 66.733.3 133.3 133.3 133.3 133.3 133.3 133.3 133.3 133.3 100.0 100.0 100.0 100.0 100.0 100.0 111.0 111.0 66.7 66.7 100.0 100.0 133.3 133.3 166.6 166.6 66.7 66.7 100.0 100.0 133.3 133.3 166.5 166.5 66.733.3 50.033.3 66.733.3 50.033.3 66.733.3 50.033.3 66.733.3 55.533.3 66.733.3 50.033.3 66.733.3 50.033.3 66.733.3 50.033.3 66.633.3 55.533.3 Description CPU ZCLK AGPPCI Bit 3 0 FS_Override Frequency Selection Source: 0 = Select through hardware strapping, latched inputs 1 = Select through I2C 0 = Normal, 1 = Spread Spectrum enable 0 = Normal, 1 = three-state all outputs Bit 2 Bit 1 Bit 0 Byte 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 0 1 0 Frequency Select Register Most significant bit of I2C Frequency Select Register Spread Spectrum Control Output Disable @Pup 0 0 0 0 Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Description Rev 1.0, November 20, 2006 Page 5 of 17 CY28372 Byte 5 (continued) Bit Bit 3 Bit 2 Bit 1 Bit 0 Byte 6 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 9 Bit Bit 7 Bit 6 Bit 5 @Pup 1 0 1 PD# Reserved 48MHz Name Power-down Enable Reserved 48-MHz Output Control Description @Pup 1 0 0 0 0 0 0 0 Name Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Pin Description Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] @Pup 1 1 1 1 1 1 1 1 PCIF1 PCIF0 PCI_5 PCI_4 PCI_3 PCI_2 PCI_1 PCI_0 Name PCIF1 Output Enable/Disable PCIF0 Output Enable/Disable PCI_5 Output Enable/Disable PCI_4 Output Enable/Disable PCI_3 Output Enable/Disable PCI_2 Output Enable/Disable PCI_1 Output Enable/Disable PCI_0 Output Enable/Disable Description @Pup 0 0 0 0 1 0 1 1 Reserved Reserved PCIF0 PCIF1 CPUT0/CPUC0 CPUT1 CPUT0/CPUC0 CPUT1 Name Reserved Reserved PCIF0 functionality when PCI_STP# is LOW 0: Free running, 1: Stop PCIF1 functionality when PCI_STP# is LOW 0: Free running, 1: Stop CPU[T/C]0 functionality when CPU_STP# is LOW 0: Free running, 1: Stop (three-state) CPUT1 functionality when CPU_STP# is LOW 0: Free running, 1: Stop (three-state) CPU[T/C]0 Output Enable/Disable CPUT1 Output Enable/Disable Description @Pup HW HW HW HW Name Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input Description Latched FS[3:0] inputs. These bits are read-only. Rev 1.0, November 20, 2006 Page 6 of 17 CY28372 Byte 9 (continued) Bit Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 1 0 0 0 0 Name 24_48MHz 24_48MHz SS2 SS1 SS0 24_48MHz Output Control 24-MHz or 48-MHz Select 0: 24MHz, 1: 48MHz Spread Spectrum control bit (0 = down spread, 1 = center spread) SS[2:0] 000 001 010 011 100 101 110 111 Spread Mode Down Down Down Down Center Center Center Center Spread% 0, -0.50 (default) +0.12, -0.62 +0.25, -0.75 +0.50, -1.00 +0.25, -0.25 +0.37, -0.37 +0.50, -0.50 +0.75, -0.75 Description Byte 10 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 11 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved 3V66 Fract_Align4 3V66 Fract_Align3 3V66 Fract_Align2 3V66 Fract_Align1 3V66 Fract_Align0 Description Vendor Test Mode (always program to 0) Vendor Test Mode (always program to 0) Vendor Test Mode (always program to 0) 3V66 Frequency Fractional Aligner: These bits determine the 3V66 fixed frequency. This option does not incorporate spread spectrum. Fract_Align3V66 (MHz)PCI (MHz) 00000 Off Off(default) 0000166.533.2 0001067.533.7 0001168.534.3 0010069.534.8 0010170.635.3 0011071.635.8 0011172.636.3 0100073.636.8 0100174.737.3 0101075.737.8 0101176.738.4 0110077.738.9 0110178.739.4 0111079.839.9 0111180.840.4 1000081.840.9 1000182.841.4 1001083.941.9 1001184.942.4 1010085.943.0 1010186.943.5 1011088.044.0 1011189.044.5 1100090.045.0 1100191.045.5 1101092.046.0 1101193.146.5 1110094.147.0 1110195.147.6 1111096.148.1 1111197.248.6 @Pup 1 1 1 1 1 1 1 1 Name IOAPIC_1 IOAPIC_0 REF_1 REF_0 ZCLK_1 ZCLK_0 AGP_1 AGP_0 Description IOAPIC_1 Output Control IOAPIC_0 Output Control REF_1 Output Control REF_0 Output Control ZCLK_1 Output Control ZCLK_0 Output Control AGP_1 Output Control AGP_0 Output Control Rev 1.0, November 20, 2006 Page 7 of 17 CY28372 Byte 12 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 @Pup 0 0 0 0 0 0 Name REF_2 Reserved Reserved DARAG2 DARAG1 DARAG0 Description REF_2 Output Control (default: off) Reserved Reserved Dial-a-Ratio AGP[0:1]. Programming these bits allow modifying the frequency ratio of the AGP(1:0), PCI(5:0) and PCIF(0:1) clocks relative to the VCO. (the ratio of AGP to PCI is retained at 2:1) DARAG[2:0] 000 001 010 011 100 101 110 111 VC0/AGP Ratio - (Frequency Selection Default) 6 8 9 10 12 12 12 Bit 1 0 Fixed_PCI_SEL Bit 0 0 Fixed_3V66_SEL PCI output frequency select mode (valid only when Fixed_3V66_SEL = 1) 0 = Use Frequency Selection Table settings 1 = Use Fractional Aligner settings (default) 3V66 and PCI output frequency select mode 0 = Use Frequency Selection Table settings (default) 1 = Use Fractional Aligner settings Byte 13 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 14 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved R5 (MSB) R4 R3 R2 R1 R0 (LSB) R & N Select Pin Description Reserved Dial-a-Frequency Control Register R These bits are for programming the PLL’s internal R register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. (should be written together with Control Register N) R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from the DAF registers into R and N. @Pup 0 0 0 0 0 0 0 0 Name Reserved N6 (MSB) N5 N4 N3 N2 N1 N0 (LSB) Description Reserved Dial-a-Frequency® Control Register N. These bits are for programming the PLL’s internal N register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. (should be written together with Control Register R) Rev 1.0, November 20, 2006 Page 8 of 17 CY28372 Dial-A-Frequency Feature SMBus Dial-a-Frequency feature is available in this device via Byte13 and Byte14. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (FS). P value may be determined from the following table. FS(4:0) 00000, 00001, 00010, 00011, 00100, 00101, 11110 00110, 00111, 10000, 10001, 10010, 10011, 10100 01000, 01001, 01010, 01011, 01100, 01101, 10101, 10110, 10111, 11001, 11010, 11011,11100, 11101 01110, 01111, 11000 11111 Table 5. Maximum Lumped Capacitive Output Loads Clock PCI, PCIF AGP 24_48MHz, 48MHz REF IOAPIC CPUT0/CPUC0 CPUT1 Max Load 20 30 20 30 20 See Figure 7 See Figure 7 Unit pF pF pF pF pF PD# (Power-down) Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD# – Assertion P 127993333 76796000 95995000 63996667 191990000 PD# CPUT0 CPUC0 PCI USB,24_48MHz REF Tri-state Tri-state Figure 1. Power-down Assertion Timing Waveforms Rev 1.0, November 20, 2006 Page 9 of 17 CY28372 PD# – Deassertion After the clock chip internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other, with the first to last active clock taking no more than two full PCI clock cycles. 1.2 ms PD# CPUT CPUC PCI 33MHz Driven Driven 3V66 USB 48MHz REF 14.318MHz Figure 2. Power Down Deassertion Timing Waveforms Table 6. PD# Functionality PD# 1 0 CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# – Assertion When CPU_STP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two rising CPUC clock edges. The final state of the stopped CPU signals is CPUT = CPUC = three-state. CPU_STP# CPUT Normal Float CPUC Normal Float AGP Normal Low PCIF/PCI Normal Low 48MHz Normal Low CPUT three-state CPUC three-state Figure 3. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles. Rev 1.0, November 20, 2006 Page 10 of 17 CY28372 PCI_STP# Assertion CPU_STP# three-state CPUT three-state CPUC The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup). The PCIF clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. CPUTint CPUCint Figure 4. CPU_STP# Deassertion Waveform t setup PCI_STP# PCIF 33M PCI 33M Figure 5. PCI_STP# Assertion Waveform PCI_STP# - Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. tsetup PCI_STP# PCIF PCI Figure 6. PCI_STP# Deassertion Waveform Rev 1.0, November 20, 2006 Page 11 of 17 CY28372 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD VDDA VIN TS TA TJ ESDHBM ØJC ØJA UL–94 MSL Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. –0.5 –0.5 –0.5 –65 0 – 2000 15 45 V–0 1 4.6 4.6 VDD + 0.5 +150 70 150 – V V VDC °C °C °C V °C/W °C/W Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Conditions Min. Max. Unit VDD, VDDA CIN COUT LIN IDD IPD CXTAL VXIH VXIL 3.3 Operating Voltage Input Pin Capacitance Output Pin Capacitance Pin Inductance Dynamic Supply Current Crystal Pin Capacitance XIN High Voltage XIN Low Voltage 3.3V ± 5% 3.135 2 3 – 3.465 5 6 7 280 1 42 VDD 0.3VDD V pF pF nH mA mA pF V V All frequencies at maximum value Measured from the XIN or XOUT pin to ground – – 30 0.7VDD 0 Power-down Supply Current PD# Asserted AC Electrical Specifications Parameter Description Conditions Crystal The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification Min. Max. Unit TDC XIN Duty Cycle 47.5 52.5 % TPERIOD T R / TF TCCJ XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter When Xin is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1- s duration CPUT0/CPUC0 Measured at crossing point VOX 69.841 – – 71.0 10.0 500 ns ns ps TDC TPERIOD TPERIOD TSKEW TCCJ CPUT0 and CPUC0 Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period Any CPU to CPU Clock Skew CPU Cycle to Cycle Jitter 45 9.8 7.35 – – 55 10.2 7.65 150 150 % ns ns ps ps Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Rev 1.0, November 20, 2006 Page 12 of 17 CY28372 AC Electrical Specifications (continued) Parameter Description Conditions Min. Max. Unit T R / TF VOX TDC TPERIOD TPERIOD TCCJ T R / TF CPUT and CPUC Rise and Fall Times Crossing Point Voltage at 0.7V Swing CPUT1 Duty Cycle 100MHz CPUT1 Period 133MHz CPUT1 Period CPUT1 Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Measured from Vol= 0.175 to Voh = 0.525V CPUT1 Measured at crossing point VOX 0.5 600 45 9.8 7.35 – 0.5 2.0 800 55 10.2 7.65 150 2.0 V/ns mv % ns ns ps V/ns Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL= 0.175 to VOH = 0.525V IOAPIC Measured at crossing point VOX TDC TPERIOD TPERIOD TSKEW THIGH TLOW TCCJ T R / TF IOAPIC Duty Cycle 100MHz IOAPIC Period 133MHz IOAPIC Period Any IOAPIC clock to any IOPIC Clock Skew IOAPIC High Time IOAPIC Low Time IOAPIC Cycle to Cycle Jitter IOAPIC Rise and Fall Times 45 69 69 – 25.5 25.3 55 70 70 250 – – 500 1.6 % ns ns ps Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from Vol= 0.175 to Voh = 0.525V AGP Measured at crossing point VOX – 0.4 ps V/ns TDC TPERIOD TPERIOD TSKEW(UNBUFFERED) AGP Duty Cycle 100-MHz AGP Period 133-MHz AGP Period 45 15.0 15.0 – 5.25 5.25 55 15.3 15.3 250 – – 250 1.6 % ns ns ps ns ns ps ns Measured at crossing point VOX Measured at crossing point VOX Any AGP clock to any AGP Clock Skew Measured at crossing point VOX AGP High Time AGP Low Time AGP Cycle to Cycle Jitter AGP Rise and Fall Times Measured at crossing point VOX Measured from Vol = 0.175 to Voh = 0.525V ZCLK Measured at crossing point VOX THIGH TLOW TCCJ T R / TF – 0.5 TDC TSKEW TCCJ T R / TF ZCLK Duty Cycle Any ZCLK clock to any ZCLK Clock Skew ZCLK Cycle to Cycle Jitter ZCLK Rise and Fall Times 45 – – 0.5 55 175 250 1.6 % ps ps ns Measured at crossing point VOX Measured at crossing point VOX Measured from Vol= 0.175 to Voh = 0.525V PCI/PCIF Measured at crossing point VOX TDC TPERIOD TPERIOD TSKEW THIGH TLOW PCI and PCIF Duty Cycle 100-MHz PCI and PCIF Period 133-MHz PCI and PCIF Period 45 30.0 30.0 – 12.0 12.0 55 – – 500 – – % ns ns ps ns ns Measured at crossing point VOX Measured at crossing point VOX Any PCI and PCIF clock to any PCI and Measured at crossing point VOX PCIF Clock Skew PCI and PCIF High Time PCI and PCIF Low Time Rev 1.0, November 20, 2006 Page 13 of 17 CY28372 AC Electrical Specifications (continued) Parameter Description Conditions Min. Max. Unit TCCJ T R / TF PCI and PCIF Cycle to Cycle Jitter PCI and PCIF Rise and Fall Times Measured at crossing point VOX Measured from Vol= 0.175 to Voh = 0.525V 48M Measurement at 1.5V – 0.5 500 2.0 ps ns TDC TPERIOD TPERIOD T R / TF TCCJ TDC TPERIOD TPERIOD T R / TF TCCJ TDC TPERIOD T R / TF TCCJ TSTABLE TSS TSH TODIS TOENB 48M Duty Cycle 133-MHz 48M Period 133-MHz 48 M Period 48M Rise and Fall Times 48M Cycle to Cycle Jitter 24M Duty Cycle 100-MHz 24M Period 133-MHz 24M Period 24M Rise and Fall Times 24M Cycle to Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter 45 20.829 20.829 1.0 – 45 41.66 41.66 1.0 – 45 69.841 1.0 – – 10.0 0 1.0 1.0 55 20.834 20.834 2.0 350 55 41.67 41.67 2.0 500 55 71.0 4.0 1000 1.5 – – 10.00 10.00 % ns ns ns ps % ns ns ns ps % ns ns ps ms ns ns ns ns Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V 24M Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V REF Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V ENABLE/DISABLE and SETUP All Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time Output Disable Delay (all outputs) Output Enable Delay (all outputs) Rev 1.0, November 20, 2006 Page 14 of 17 CY28372 Test and Measurement Set-up For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. VDD_CPU T PCB C P U T /C 5pF M eas urem ent P o int V D D _C P U TPCB CPUCS 5pF M ea surem e nt P oint Figure 7. CPUCLK Test Load Configuration O u tp u t u n d e r T e s t P ro b e Load Cap 3 .3 V s ig n a l s tD C - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V Tr Tf Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement) Table 7. Group Timing Relationship and Tolerances Offset (Typical) Tolerance (or Range) Conditions Notes CPU to AGP CPU to Z CPU to PCI 2 ns 2 ns 2 ns 1 – 4 ns 1 – 4 ns 1 – 4 ns CPU leads CPU leads CPU leads – – – Layout Example Rev 1.0, November 20, 2006 Page 15 of 17 CY28372 FB C1 G G C2 VDD33 VDD25 FB C2 G G C1 G C3 C3 G C3 G C3 G 1V 2 3 4 5 6 7 8 9 10 11 V 12 13 V 14 15 16 17 18 19 V 20 21 22 23 24 G G G G G G G G G 48 47 46 45 44 43 V 42 41 40 39 V 38 37 V 36 35 34 33 32 31 30 V 29 V 28 27 26 25 V @ 100 MHz) G C3 G C3 G C3 G C3 G FB = Dale ILB1206 - 300 (300 CY28372 C3 G G C3 Cermaic Caps C1 = 10 - 22 µF G = VIA to GND plane layer C3 = .1 F V = VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = .1- f ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 C2 = .005 µF Rev 1.0, November 20, 2006 Page 16 of 17 CY28372 Ordering Information Ordering Code Package Type Operating Range CY28372OC CY28372OCT Lead Free 48-pin Small Shrunk Outline Package (SSOP) 48-pin Small Shrunk Outline Package (SSOP) – Tape and Reel 48-pin Small Shrunk Outline Package (SSOP) 48-pin Small Shrunk Outline Package (SSOP) – Tape and Reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C CY28372OXC CY28372OXCT Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 17 of 17