CY28378OC

CY28378 FTG for Pentium 4® and Intel® 845 Series Chipset Features • Compatible with Intel® CK-Titan and CK-408 Clock Synthesizer/Driver specifications • System frequency synthesizer for Intel Brookdale 845 and Brookdale – G Pentium 4® chipsets • Programmable clock output frequency with less than 1-MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when Watchdog timer time-out • Programmable 3V66 and PCI output frequency mode • Capable of generating system RESET after a Watchdog timer time-out or a change in output frequency via SMBus interface occurs • Support SMBus byte read/write and block read/ write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP Table 1. Frequency Table CPU x3 3V66 x4 PCI x 10 REF x2 48M x1 24_48M x1 Block Diagram X1 X2 Pin Configuration[1] VDD_REF REF0:1 XTAL OSC PLL 1 PLL Ref Freq Divider Network VDD_CPU *MULTSEL1/REF1 CPUT[0:1], CPUC[0:1], VDD_REF CPU_ITP, CPU_ITP# *FS0:4 VTT_PWRGD# *MULTSEL0:1 PLL2 Fract. Aligner VDD_3V66 3V66_0:2 VDD_PCI PCI_F0:2 2 PCI0:6 VDD_48MHz 3V66_3/48MHz_1 VDD_48MHz 48MHz_0 PWRDWN# 24_48MHz 2 SDATA SCLK SMBus Logic X1 X2 GND_PCI *FS2/PCI_F0 *FS3/PCI_F1 PCI_F2 VDD_PCI *FS4/PCI0 PCI1 PCI2 GND_PCI PCI3 PCI4 PCI5 PCI6 VDD_PCI VTT_PWRGD# RESET# GND_48MHz *FS0/48MHz_0 *FS1/24_48MHz VDD_48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/MULTSEL0** GND_REF VDD_CPU CPU_ITP CPU_ITP# GND_CPU PWRDWN#* CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 GNDC_CPU IREF VDD_CORE GND_CORE VDD_3V66 3V66_0 3V66_1 GND_3V66 3V66_2 3V66_3/48MHz_1 SCLK SDATA ~ CY28378 RESET# SSOP-48 Note: 1. Signals marked with ‘*’ and ‘**’ have internal pull-up and pull-down resistors, respectively. Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 21 www.SpectraLinear.com CY28378 Pin Description Pin # 3 X1 Name Type I Description Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF 150k internal pull down. Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF 150k internal pull up. CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or through serial input interface. 66MHz Clock Outputs: 3.3V fixed 66-MHz clock. Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. 150k internal pull up. Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Table 2. 150k internal pull up. Free-running PCI Output 2: 3.3V free-running PCI output. PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. 150k internal pull up. PCI Clock Output 1 to 6: 3.3V PCI clock outputs. 48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. This output will be used as the reference clock for USB host controller in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the VCH reference clock. 150k internal pull up. 4 48 X2 REF0/MULTSEL0 O I/O 1 REF1/MULTSEL1 I/O 41, 38, 40, 37 44, 45 31, 30, 28 6 CPUT(0:1), CPUC(0:1) CPU_ITP, CPU_ITP# 3V66_0:2 PCI_F0/FS2 O O O I/O 7 PCI_F1/FS3 I/O 8 10 PCI_F2 PCI0/FS4 O I/O 11, 12, 14, 15, 16, 17 22 PCI(1:6) 48MHz_0/FS0 O I/O Rev 1.0, November 20, 2006 Page 2 of 21 CY28378 Pin Description Pin # 23 Name 24_48MHz/FS1 Type I/O Description 24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. This output will be used as the reference clock for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the reference clock for both USB host controller and SIO devices. We recommend system designer to configure this output as 48 MHz and “HIGH Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively.150k internal pull up. 48MHz or 66MHz Output: 3.3V output. Power Down Control: 3.3V LVTTL compatible input that places the device in power down mode when held low. 150k internal pull up. SMBus Clock Input: Clock pin for serial interface. SMBus Data Input: Data pin for serial interface. Current Reference for CPU Output: A precision resistor is attached to this pin which is connected to the internal current reference. Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input. VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 27 42 26 25 20 35 19 3V66_3/48MHz_1 PWRDWN# SCLK SDATA RESET# IREF VTT_PWRGD# O I I I/O I I O (open-drain) System Reset Output: Open-drain system reset output. 2, 9, 18, 24, 32, 39, VDD_REF, 46 VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU 5, 13, 21, 29, 36, 43, 47 GND_PCI, GND_48MHz, GND_3V66, GND_CPU, GND_REF, VDD_CORE GND_CORE P G Ground Connection: Connect all ground pins to the common system ground plane. 34 33 P G 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. Analog Ground Connection: Ground for core logic, PLL circuitry. Rev 1.0, November 20, 2006 Page 3 of 21 CY28378 Table 2. Frequency Selection Table Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 100.7 100.9 108.0 101.2 114.0 117.0 120.0 123.0 125.7 130.3 133.9 134.2 134.5 148.0 152.0 156.0 160.0 164.0 167.4 170.0 175.0 180.0 185.0 190.0 166.8 100.2 133.6 200.4 166.6 100.0 200.0 133.3 3V66 67.1 67.3 72.0 67.5 76.0 78.0 80.0 82.0 62.9 65.1 67.0 67.1 67.3 74.0 76.0 78.0 80.0 82.0 66.9 68.0 70.0 72.0 74.0 76.0 66.7 66.8 66.8 66.8 66.6 66.6 66.6 66.6 PCI 33.6 33.6 36.0 33.7 38.0 39.0 40.0 41.0 31.4 32.6 33.5 33.6 33.6 37.0 38.0 39.0 40.0 41.0 33.5 34.0 35.0 36.0 37.0 38.0 33.4 33.4 33.4 33.4 33.3 33.3 33.3 33.3 402.80 403.60 432.00 404.80 456.00 468.00 480.00 492.00 377.12 390.80 401.70 402.60 403.50 444.00 456.00 468.00 480.00 492.00 334.80 340.00 350.00 360.00 370.00 380.00 333.60 400.80 400.80 400.80 333.33 400.00 400.00 400.00 Output Frequency VCO Freq. PLL Gear Constants (G) 47.99750 47.99750 47.99750 47.99750 47.99750 47.99750 47.99750 47.99750 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 95.99500 95.99500 95.99500 95.99500 95.99500 95.99500 95.99500 47.99750 63.99667 95.99500 95.99500 47.99750 95.99500 63.99667 Swing Select Functions MULTSEL1 0 1 MULTSEL0 0 0 Board Target Trace/Term Z 50 50 Reference R, IREF = VDD/(3*Rr) Output Current IOH = 4*Iref IOH = 6*Iref VOH @ Z 1.0V @ 50 0.7V @ 50 Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface (SDI), various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. Rev 1.0, November 20, 2006 Page 4 of 21 CY28378 The register associated with the SDI initializes to it’s default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3. Command Code Definition Bit 7 6:0 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be ‘0000000’. Descriptions Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 Bit '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave ...................... Data Byte (N–1) –8 bits Acknowledge from slave Data Byte N –8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 Bit '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop Block Read Protocol Description Rev 1.0, November 20, 2006 Page 5 of 21 CY28378 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Not Acknowledge Stop Byte Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Byte Configuration Map Byte 0 Bit Bit 7 Bit 6 Bit 5 @Pup 0 0 0 Name Spread Select2 Spread Select1 Spread Select0 ‘000’ = OFF ‘001’ = +0.12, – 0.62% ‘010’ = +0.25, – 0.75% ‘011’ = +0.50, – 1.00% ‘100’ = ± 0.25% ‘101’ = +0.00, – 0.50% ‘110’ = ±0.5% ‘111’ = ±0.38% SW Frequency selection bits. See Table 2. Description Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 @Pup 1 1 1 1 1 1 1 1 SEL4 SEL3 SEL2 SEL1 SEL0 Name CPUT1, CPUC1 CPUT0, CPUC0 48MHz 24_48MHz 3V66_3 3V66_2 3V66_1 3V66_0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Rev 1.0, November 20, 2006 Page 6 of 21 CY28378 Byte 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 4 Bit Bit 7 @pup 0 1 1 1 1 1 1 1 @Pup 1 1 1 0 1 0 1 1 @Pup 0 PCI_F2 PCI_F1 PCI_F0 Reserved CPU_ITP, CPU_ITP# Reserved REF1 REF0 Name MULTSEL_Override PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) Pin Description This bit control the selection of IREF multiple. 0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins 1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6]. IREF multiplier 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF Reserved Reserved Reserved Reserved Vendor Test Mode (always program to 0) Pin Description Latched FS[4:0] inputs. These bits are read only. Name Reserved Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description Pin Description Bit 6 Bit 5 HW HW SW_MULTSEL1 SW_MULTSEL0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 @Pup HW HW HW HW HW 0 0 1 Reserved Reserved Reserved Reserved Reserved Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input FS_Override SEL 3V66 SEL 48MHZ 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings 0 = 48-MHz output on pin 27, 1 = 66-MHz output on pin 27 0 = 24-MHz,1 = 48-MHz Rev 1.0, November 20, 2006 Page 7 of 21 CY28378 Byte 6 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 0 0 0 0 0 0 0 0 @Pup 0 0 0 1 1 0 0 0 Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Name Reserved Reserved Reserved Reserved Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Pin Description Vendor Test Mode (always program to 0) Vendor Test Mode (always program to 0) Vendor Test Mode (always program to 0) Vendor Test Mode (always program to 0) Pin Description 3V66 Fract_Align3 3V66 Frequency Fractional Aligner: These bits determine the 3V66 fixed frequency. This 000166.533.2 3V66 Fract_Align2 option does not incorporate spread spectrum and is enabled through Byte10, bit 4 3V66 Fract_Align1 3V66 Fract_Align0 001067.533.7 001168.534.3 010069.534.8 010170.635.3 011071.635.8 011172.636.3 100073.636.8 100174.737.3 101075.737.8 101176.738.4 110077.738.9 Byte 8 Bit Bit 7 Bit 6 @Pup 0 0 Name WD_Alarm Frequency_Revert Pin Description This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears the WD_TIMER time stamp This bit allows setting the Revert Frequency once the system is rebooted 0: Hardware 1: Last Programmed Reserved Watchdog timer time stamp selection: 0000: Off 0001: 1 second 0010: 2 seconds . . . 1110: 14 seconds 1111: 15 seconds Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 0 Reserved WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 Bit 0 1 Reserved Reserved Rev 1.0, November 20, 2006 Page 8 of 21 CY28378 Byte 9 Bit Bit 7 @Pup 0 Name 48MHz_DRV Pin Description 48MHz and 24_48MHz clock output drive strength 0 = Normal 1 = High Drive (Recommend to set to high drive if this output is being used to drive both USB and SIO devices in Intel Brookdale – G platforms) PCI clock output drive strength 0 = Normal 1 = High Drive 3V66 clock output drive strength 0 = Normal 1 = High Drive Reserved Reserved Reserved Reserved Reserved Name CPU_Skew2 CPU_Skew1 CPU_Skew0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 3V66 and PCI output frequency select mode 0 = Set according to Frequency Selection Table 1 = Set according to Fractional Aligner settings Bit 6 0 PCI_DRV Bit 5 0 3V66_DRV Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 10 Bit Bit 7 Bit 6 Bit 5 0 0 0 0 0 @Pup 0 0 0 Reserved Reserved Reserved Reserved Reserved Pin Description Bit 4 0 Fixed 3V66_SEL Bit 3 Bit 2 0 0 PCI_Skew1 PCI_Skew0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps 3V66 skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 1 Bit 0 0 0 3V66_Skew1 3V66_Skew0 Byte 11 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Rev 1.0, November 20, 2006 Page 9 of 21 CY28378 Byte 12 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 13 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 14 Bit Bit 7 @Pup 0 0 0 0 0 0 0 0 @Pup 0 0 0 0 0 0 0 0 @Pup 0 Reserved CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Name Pro_Freq_EN Pin Description Programmable output frequencies enabled 0 = disabled 1 = enabled Reserved If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[6:0] and CPU_FSEL_M[5:0] will be used to determine the CPU output frequency. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[6:0] and CPU_FSEL_M[5:0] will be used to determine the CPU output frequency. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Pin Description Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 Reserved CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 Watchdog Self Recovery Sequence This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. When the system sends an SMBus command requesting a frequency change through the Dial-a-Frequency Control Registers, it must have previously sent a command to the Watchdog Timer to select which time out stamp the Watchdog must perform, otherwise the System Self Recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in the Watchdog Timer bits (reprogram to 0000) before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. The Watchdog timer will also be triggered if you program the software frequency select bits (FSEL) to a new frequency selection. If the Watchdog times out before the new SMBus reprograms the Watchdog Timer bits to (0000), then this device will send a low system reset pulse, on SRESET# and changes WD Time-out bit to “1.” Rev 1.0, November 20, 2006 Page 10 of 21 CY28378 RESET W ATCHDOG TIMER Set WD(0:3) Bits = 0 INITIALIZE W ATCHDOG TIMER Set Frequency Revert Bit Set WD(0:3) = (# of Sec ) x 2 SET SOFTW ARE FSEL Set SW Freq_Sel = 1 Set FS(0:4) SET DIAL-A-FREQUENCY Load M and N Registers Set Pro_Freq_EN = 1 Wait for 6msec For Clock Output to Ramp to Target Frequency Hang? N CLEAR W D Set WD(0:3) Bits = 0 Exit Y W ATCHDOG TIMEOUT Frequency Revert Bit = 0 Set Frequency to FS_HW_Latched Frequency Revert Bit = 1 Set Frequency to FS_SW Set SRESET# = 0 for 6 msec Reset Figure 1. Watchdog Flowchart Program the CPU output frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * N/M. “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 2. The ratio of N and M need to be greater than “1” [N/M> 1]. The following table lists set of N and M values for different frequency output ranges. This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 66 – 127 128 – 203 Gear Constants 47.99750 63.99667 Fixed Value for M-Value Register 48 40 Range of N-Value Register for Different CPU Frequency 66 – 127 80 – 127 Rev 1.0, November 20, 2006 Page 11 of 21 CY28378 Table 7. Maximum Lumped Capacitive Output Loads Clock PCI, PCI_F 3V66 48M_24MHz, 48MHz REF CPUT/C CPU_ITP Table 8. Group Timing Relationship and Tolerances Offset 3V66 to PCI Typical 2.5 ns Tolerance (or Range) 1.5 – 3.5 ns Conditions 3V66 leads Notes See Note 2 Max Load 20 30 20 30 See Figure 4 Units pF pF pF pF pF PD# (Power-down) Clarification The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# PD# – Assertion PWRDWN# CPUT, 133MHz CPUC, 133MHz AGP, 66MHz USB, 48MHz PCI, 33MHz REF, 14.131818 is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low “stopped” state. Figure 2. Power-down Assertion Timing Waveforms Rev 1.0, November 20, 2006 Page 12 of 21 CY28378 PD# – Deassertion Tstable 0.25mS VDDA = 2.0V Sample Inputs straps Wait for 1.146ms S0 S3 VDDA = off Power Off Normal Operation VTT_PWRGD# = toggle Enable Outputs Figure 7. Clock Generator Power-up/Run State Diagram Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Note: 6. Device is not affected, VTT_PWRGD# is ignored. Rev 1.0, November 20, 2006 Page 17 of 21 CY28378 Switching Waveforms (continued) Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD 0V t2 t3 OUTPUT CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 PCI-PCI Clock Skew PCI PCI t6 3V66-PCI Clock Skew 3V66 PCI t7 Rev 1.0, November 20, 2006 Page 18 of 21 CY28378 Switching Waveforms (continued) CPU Clock Cycle-Cycle Jitter t8A Host_b Host t8B Cycle-Cycle Clock Jitter t9A t9B CLK Layout Example Rev 1.0, November 20, 2006 Page 19 of 21 CY28378 +3.3V Supply FB VDDQ3 .005 F C3 G G G G G VDDQ3 5 1 2 VG 3 4 5G 6 7 8G 9V G 10 11 12 13 G 14 15 16 17 G 18 V 19 G 20 21 G 22 23 24 * G G 48 47 V 46 G 45 44 G 43 42 41 G 40 V 39 G 38 37 G 36 G 35 V 34 G 3 V 32 G 31 30 G 29 28 27 26 G 25 G G G CY28378 G G C5 G G C6 FB = Dale ILB1206 - 300 (300 Cermaic Caps C3 = 10 - 22 µF G = VIA to GND plane layer @ 100 MHz) C4 = .005 µF C5 = 10 F C6 = .1 F V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = .1 f ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 Rev 1.0, November 20, 2006 Page 20 of 21 CY28378 Ordering Information Ordering Code Package Type Operating Range CY28378OC CY28378OCT 48-pin Small Shrunk Outline Package (SSOP) 48-pin Small Shrunk Outline Package (SSOP) –Tape and Reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C Package Diagram 48-Lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 21 of 21