CY28409ZC

CY28409 Clock Synthesizer with Differential SRC and CPU Outputs Features • Supports Intel Pentium 4-type CPUs • Selectable CPU frequencies • 3.3V power supply • Ten copies of PCI clocks • Five copies of 3V66 with one optional VCH • Two copies 48 MHz USB clocks CPU x3 SRC x1 3V66 x5 PCI x 10 REF x2 48M x2 • Three differential CPU clock pairs • One differential SRC clock • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum EMI reduction • 56-pin SSOP and TSSOP packages Block Diagram XIN XOUT CPU_STP# PCI_STP# FS_[A:B] VTT_PWRGD# IREF VDD_3V66 3V66_[0:3] Pin Configuration VDD_REF REF0:1 [1] XTAL OSC PLL1 ~ PLL Ref Freq Divider Network VDD_CPU CPUT[0:2], CPUC[0:2] VDD_SRC SRCT, SRCC PLL2 2 VDD_PCI PCIF[0:2] PCI[0:6] 3V66_4/VCH VDD_48MHz DOT_48 USB_48 PD# SDATA SCLK I2C Logic REF_0 REF_1 VDD_REF XIN XOUT VSS_REF PCIF0 PCIF1 PCIF2 VDD_PCI VSS_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI VSS_PCI PCI4 PCI5 PCI6 PD# 3V66_0 3V66_1 VDD_3V66 VSS_3V66 3V66_2 3V66_3 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS_B VDD_A VSS_A VSS_IREF IREF FS_A CPU_STP# PCI_STP# VDD_CPU CPUT2 CPUC2 VSS_CPU CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS_SRC SRCT SRCC VDD_SRC VTT_PWRGD# VDD_48 VSS_48 DOT_48 USB_48 SDATA 3V66_4/VCH 56 SSOP/TSSOP CY28409 Note: 1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively. Rev 1.0, November 22, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 16 www.SpectraLinear.com CY28409 Pin Description Pin No. 1, 2 4 XIN Name REF(0:1) Type I Description Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. O, SE Reference Clock. 3.3V 14.318-MHz clock output. 5 41,44,47 40,43,46 38, 37 22,23,26,27 29 7,8,9 12,13,14, 15,18,19,20 31, 32 51,56 52 21 50 49 35 30 28 53 55 54 42,48 45 36 39 34 33 10,16 11,17 24 25 3 6 XOUT CPUT(0:2) CPUC(0:2) SRCT, SRCC 3V66(0:3) 3V66_4VCH PCIF(0:2) PCI(0:6) USB_48 DOT_48 FS_A, FS_B IREF PD# CPU_STP# PCI_STP# VTT_PWRGD# SDATA SCLK VSS_IREF VDD_A VSS_A VDD_CPU VSS_CPU VDD_SRC VSS_SRC VDD_48 VSS_48 VDD_PCI VSS_PCI VDD_3V66 VSS_3V66 VDD_REF VSS_REF O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output. O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration. O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration. O, DIF Differential serial reference clock. O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. O, SE 48-/66-MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz. O, SE Free-running PCI Output. 33-MHz clocks divided down from 3V66. O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66. O, SE Fixed 48-MHz clock output. O, SE Fixed 48-MHz clock output. I I I, PU I, PU I, PU I I/O I GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND 3.3V LVTTL input for CPU frequency selection. Current Reference. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for Power-Down# active LOW. 3.3V LVTTL input for CPU_STP# active LOW. 3.3V LVTTL input for PCI_STP# active LOW. 3.3V LVTTL input is a level sensitive strobe used to latch the FS_A and FS_B inputs (active LOW). SMBus-compatible SDATA. SMBus-compatible SCLOCK. Ground for current reference. 3.3V power supply for PLL. Ground for PLL. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. Rev 1.0, November 22, 2006 Page 2 of 16 CY28409 Table 1. Frequency Select Table (FS_A, FS_B) FS_A 0 0 0 1 1 FS_B 0 MID 1 0 MID CPU 100 MHz REF/N 200 MHz 133 MHz Hi-Z SRC 100/200 MHz REF/N 100/200 MHz 100/200 MHz Hi-Z 3V66 66 MHz REF/N 66 MHz 66 MHz Hi-Z PCIF/PCI 33 MHz REF/N 33 MHz 33 MHz Hi-Z REF0 14.3 MHz REF/N 14.3 MHz 14.3 MHz Hi-Z REF1 14.31 MHz REF/N 14.31 MHz 14.31 MHz Hi-Z USB/DOT 48 MHz REF/N 48 MHz 48 MHz Hi-Z Table 2. Frequency Select Table (FS_A, FS_B) SMBus Bit 5 of Byte 6 = 1 FS_A 0 0 1 FS_B 0 1 0 CPU 200 MHz 400 MHz 266 MHz SRC 100/200 MHz 100/200 MHz 100/200 MHz 3V66 66 MHz 66 MHz 66 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz REF0 14.3 MHz 14.3 MHz 14.3 MHz REF1 14.31 MHz 14.31 MHz 14.31 MHz USB/DOT 48 MHz 48 MHz 48 MHz Frequency Select Pins (FS_A, FS_B) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A and FS_B inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A and FS_B input values. For all logic levels of FS_A and FS_B except MID, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled LOW, all further VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In the case where FS_B is at mid level when VTT_PWRGD# is sampled LOW, the clock chip will assume “Test Clock Mode.” Once “Test Clock Mode” has been invoked, all further FS_B transitions will be ignored and FS_A will asynchronously select between the Hi-Z and REF/N mode. Exiting test mode is accomplished by cycling power with FS_B in a HIGH or LOW state. Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Table 3. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Block Read Protocol Description Rev 1.0, November 22, 2006 Page 3 of 16 CY28409 Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave ...................... Data Byte (N–1) – 8 bits Acknowledge from slave Data Byte N – 8 bits Acknowledge from slave Stop Description Bit 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... Table 5. Byte Read and Byte Write protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Acknowledge from master Stop Byte Read Protocol Description Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte N from slave – 8 bits Acknowledge from master Stop Block Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Control Registers Byte 0:Control Register 0 Bit 7 6 @Pup 0 1 Reserved PCIF PCI Reserved Reserved Name Reserved, Set = 0 PCI Drive Strength Override 0 = Force All PCI and PCIF Outputs to Low Drive Strength 1 = Force All PCI and PCIF Outputs to High Drive Strength Reserved, Set = 0 Reserved, Set = 0 Description 5 4 0 0 Rev 1.0, November 22, 2006 Page 4 of 16 CY28409 Byte 0:Control Register 0 (continued) Bit 3 2 1 0 @Pup Externally Selected Externally Selected Externally Selected Externally Selected Name PCI_STP# CPU_STP# FS_B FS_A Description PCI_STP# reflects the current value of the external PCI_STP# pin. 0 = PCI_STP# pin is LOW. CPU_STP# reflects the current value of the external CPU_STP# pin. 0 = CPU_STP# pin is LOW. FS_B reflects the value of the FS_B pin sampled on power-up. FS_A reflects the value of the FS_A pin sampled on power-up. Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Name SRCT, SRCC SRCT, SRCC Reserved Reserved Reserved CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 Description Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRCT, SRCC SRCT, SRCC CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 Description SRCT/C Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down SRCT/C Stop Drive Mode 0 = Driven during PCI_STP, 1 = Three-state during PCI_STP CPUT/C2 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down CPUT/C1 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down CPUT/C0 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down CPUT/C2 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped CPUT/C1 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped CPUT/C0 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped Byte 3: Control Register 3 Bit 7 @Pup 1 Name SW PCI STOP Description SW PCI_STP Function 0= PCI_STP assert, 1= PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses. PCI6 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI6 Rev 1.0, November 22, 2006 Page 5 of 16 CY28409 Byte 3: Control Register 3 (continued) Bit 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled Description Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 1 1 1 USB_48 USB_48 PCIF2 PCIF1 PCIF0 PCIF2 PCIF1 PCIF0 Name Description USB_48 Drive Strength 0 = High drive strength, 1 = Low drive strength USB_48 Output Enable 0 = Disabled, 1 = Enabled Allow control of PCIF2 with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled PCIF0 Output Enable 0 = Disabled, 1 = Enabled Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 1 1 1 1 1 DOT_48 Reserved 3V66_4/VCH 3V66_4/VCH 3V66_3 3V66_2 3V66_1 3V66_0 Name DOT_48 Output Enable 0 = Disabled, 1 = Enabled Reserved, Set = 1 VCH Select 66-MHz/48-MHz 0 = 3V66 mode, 1 = VCH (48-MHz) mode 3V66_4/VCH Output Enable 0 = Disabled, 1 = Enabled 3V66_3 Output Enable 0 = Disabled, 1 = Enabled 3V66_2 Output Enable 0 = Disabled, 1 = Enabled 3V66_1 Output Enable 0 = Disabled, 1 = Enabled 3V66_0 Output Enable 0 = Disabled, 1 = Enabled Description Rev 1.0, November 22, 2006 Page 6 of 16 CY28409 Byte 6: Control Register 6 Bit 7 6 5 @Pup 0 0 0 Reserved Reserved CPUC0, CPUT0 CPUC1, CPUT1 CPUC2, CPUT2 SRCT, SRCC Reserved PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP REF_1 REF_0 Name Reserved, Set = 0 Reserved, Set = 0 FS_A & FS_B Operation 0 = Normal, 1 = Test mode SRC Frequency Select 0 = 100 MHz, 1 = 200 MHz Reserved, Set = 0 Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Description 4 3 2 0 0 0 1 0 1 1 REF_1 Output Enable 0 = Disabled, 1 = Enabled REF_0 Output Enable 0 = Disabled, 1 = Enabled Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 1 0 0 0 Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Table 6. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm Crystal Recommendations The CY28409 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28409 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1. Crystal Capacitive Clarification Rev 1.0, November 22, 2006 Page 7 of 16 CY28409 Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. C lo c k C h ip (C Y 2 8 4 0 9 ) C i1 C i2 P in 3 to 6 p Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) 1 CLe = 1 1 ( Ce1 + Cs1 + Ci1 + Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) PD# (Power-down) Clarification C s1 X1 X2 C s2 T ra c e 2 .8 p F XTAL Ce1 C e2 T r im 33pF Figure 2. Crystal Loading Example The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so as not to cause glitches while changing to the low ‘stopped’ state. PD# Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock then all clock outputs (except CPU) clocks must be held LOW on their next HIGH-to-LOW transition. CPU clocks must be held with CPU clock pin driven HIGH with a value of 2 x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF Figure 3. Power-down Assertion Timing Waveform Rev 1.0, November 22, 2006 Page 8 of 16 CY28409 PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two rising edges of the internal CPUT clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. Tstable 200 mV Figure 6. CPU_STP# Deassertion Waveform Rev 1.0, November 22, 2006 Page 9 of 16 CY28409 PCI_STP# Assertion[2] The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 7.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free-running. Tsu PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. PCI_STP# PCI_F PCI SRC 100MHz Figure 7. PCI_STP# Assertion Waveform Tsu Tdrive_SRC PCI_STP# PCI_F PCI SRC 100MHz Figure 8. PCI_STP# Deassertion Waveform Note: 2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running. Rev 1.0, November 22, 2006 Page 10 of 16 CY28409 FS_A, FS_B VTT_PWRGD# PWRGD_VRM VDD Clock Gen Clock State State 0 0.2-0.3 ms Delay State 1 Wait for VTT_PWRGD# Sample Sels State 2 State 3 Device is not affected, VTT_PWRGD# is ignored Clock Outputs Off On Clock VCO Off On Figure 9. VTT_PWRGD# Timing Diagram S1 S2 VTT_PWRGD# = Low Delay >0.25 ms VDDA = 2.0V Sample Inputs straps Wait for