CY28441

CY28441 Clock Generator for Intel Alviso Chipset Features • Compliant to Intel CK410M • Supports Intel Pentium®-M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks • SRC clocks independently stoppable through CLKREQ#[A:B] CPU x2 / x3 SRC x6 / x7 PCI x6 REF x1 DOT96 x1 USB_48 x1 • 33 MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin TSSOP package Block Diagram XIN XOUT CPU_STP# PCI_STP# CLKREQ[A:B]# FS_[C:A] VTT_PWRGD# IREF Pin Configuration VDD_PCI VSS_PCI PCI3 VDD_CPU PCI4 CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI5 VDD_SRC VSS_PCI SRCT[0:5], SRCC[0:5] VDD_PCI PCIF0/ITP_EN PCIF1 VTT_PWRGD#/PD VDD_PCI VDD_48 PCI[2:5] USB_48/FS_A VDD_PCIF VSS_48 PCIF[0:1] DOT96T DOT96C VDD_48 MHz FS_B/TEST_MODE DOT96T SRCT0 DOT96C SRCC0 USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4_SATAT SRC4_SATAC VDD_SRC VDD_REF REF XTAL OSC PLL1 PLL Ref Freq Divider Network PD PLL2 SDATA SCLK I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2 PCI_STP# CPU_STP# FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC CLKREQA# CLKREQB# SRCT5 SRCC5 VSS_SRC 56 TSSOP CY28441 Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 19 www.SpectraLinear.com CY28441 Pin Description Pin No. 33, 32 Name CLKREQA#, CLKREQB#, CPU_STP# CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 DOT96T, DOT96C FS_A/USB_48 FS_B/TEST_MODE Type I, PU Description 3.3V LVTTL input for enabling assigned SRC clock, active LOW. CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte 8. 3.3V LVTTL input for CPU_STP# active LOW. 54 36, 35 I, PU 44, 43, 41, 40 CPUT/C O, DIF Differential CPU clock outputs. O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Fixed 96-MHz clock output. I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z, 1 = Ref/N Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. 3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled to greater than 2.0V when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. A precision resistor is attached to this pin, which is connected to the internal current reference. 3.3V LVTTL input for PCI_STP# active LOW. 14, 15 12 16 53 FS_C/TEST_SEL I 39 56, 3, 4, 5 55 8 9 52 46 47 26, 27 IREF PCI PCI_STP# PCIF0/ITP_EN PCIF1 REF SCLK SDATA SRC4_SATAT, SRC4_SATAC I O, SE 33 MHz clocks. I, PU I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 O, SE 33 MHz clock. O, SE Reference clock. 3.3V 14.318-MHz clock output. I I/O SMBus-compatible SCLOCK. SMBus-compatible SDATA. O, DIF Differential serial reference clock. Recommended output for SATA. O, DIF Differential serial reference clocks. SRCT/C 24, 25, 22, 23, 19, 20, 17, 18, 31, 30 11 42 1,7 48 21, 28, 34 37 13 45 2,6 51 29 38 10 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSSA VTT_PWRGD#/PD PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND I 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for PLL. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for PLL. 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). Rev 1.0, November 21, 2006 Page 2 of 19 CY28441 Pin Description Pin No. 50 49 XIN XOUT Name Type I 14.318-MHz crystal input. O, SE 14.318-MHz crystal output. initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Description Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B and FS_C input values. For all logic levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B and FS_C transitions will be ignored, except in test mode. See Table 1. Data Protocol The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The Block Write and Block Read protocol is outlined in Table 3 while Table 4 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h). Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 1. Frequency Select Table FS_A, FS_B and FS_C FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100 MHz 133 MHz SRC 100 MHz 100 MHz PCIF/PCI 33 MHz 33 MHz REF0 14.318 MHz 14.318 MHz DOT96 96 MHz 96 MHz USB 48 MHz 48 MHz RESERVED Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block Read or Block Write operation, 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Description Bit 1 8:2 9 10 18:11 19 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Block Read Protocol Description Rev 1.0, November 21, 2006 Page 3 of 19 CY28441 Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 27:20 28 36:29 37 45:38 46 .... .... .... .... Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N –8 bits Acknowledge from slave Stop Description Bit 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge Stop Byte Read Protocol Description Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave – 8 bits NOT Acknowledge Stop Block Read Protocol Description Control Registers Byte 0:Control Register 0 Bit 7 6 5 4 3 @Pup 1 1 1 1 1 Name CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 RESERVED SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 Description CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable RESERVED SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable Rev 1.0, November 21, 2006 Page 4 of 19 CY28441 Byte 0:Control Register 0 (continued) Bit 2 1 0 @Pup 1 1 1 Name SRC[T/C]2 SRC[T/C]1 SRC[T/C]0 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 1 1 0 Name PCIF0 DOT_96T/C USB_48 REF Reserved CPU[T/C]1 CPU[T/C]0 CPUT/C SRCT/C PCIF PCI PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled Reserved CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on Description Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI5 PCI4 PCI3 PCI2 PCI Reserved Reserved PCIF1 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI Output Drive strength 0 = Low drive 1 = High drive Reserved, Set = 1 Reserved, Set = 1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description Byte 3: Control Register 3 Bit 7 6 5 @Pup 0 0 0 Name SRC7 RESERVED SRC5 Description Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Rev 1.0, November 21, 2006 Page 5 of 19 CY28441 Byte 3: Control Register 3 (continued) Bit 4 3 2 1 0 @Pup 0 0 0 0 0 Name SRC4 SRC3 SRC2 SRC1 SRC0 Description Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]0 with assertion of PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name Reserved DOT96T/C Reserved PCIF1 PCIF0 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Reserved, Set = 0 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z Reserved, Set = 0 Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Description Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC[T/C][7:0] CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 SRC[T/C][7:0] CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Description SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted Rev 1.0, November 21, 2006 Page 6 of 19 CY28441 Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 0 1 1 Reserved REF PCIF, SRC, PCI Name REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Hi-Z mode, Reserved, Set = 0 REF Output Drive Strength 0 = 1X, 1 = 2X SW PCI_STP Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during VTT_PWRGD# assertion FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during VTT_PWRGD# assertion FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during VTT_PWRGD# assertion Description 2 1 0 Externally selected Externally selected Externally selected CPUT/C CPUT/C CPUT/C Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description BYTE 8: CLKREQ Control Register Bit 7 6 @Pup 0 1 Reserved CLKREQ#B Name Reserved SRC[T/C]5 CLKREQ#B control 1 = SRC[T/C]5 stoppable by CLKREQ#B pin 0 = SRC[T/C]5 not controlled by CLKREQ#B pin SRC[T/C]3 CLKREQ#B control 1 = SRC[T/C]3 stoppable by CLKREQ#B pin 0 = SRC[T/C]3 not controlled by CLKREQ#B pin SRC[T/C]1 CLKREQ#B control 1 = SRC[T/C]1 stoppable by CLKREQ#B pin 0 = SRC[T/C]1 not controlled by CLKREQ#B pin Reserved SRC[T/C]4 CLKREQ#A control 1 = SRC[T/C]4 stoppable by CLKREQ#A pin 0 = SRC[T/C]4 not controlled by CLKREQ#A pin SRC[T/C]2 CLKREQ#A control 1 = SRC[T/C]2 stoppable by CLKREQ#A pin 0 = SRC[T/C]2 not controlled by CLKREQ#A pin Description 5 0 CLKREQ#B 4 0 CLKREQ#B 3 2 0 1 Reserved CLKREQ#A 1 0 CLKREQ#A Rev 1.0, November 21, 2006 Page 7 of 19 CY28441 BYTE 8: CLKREQ Control Register Bit 0 @Pup 0 Name CLKREQ#A Description SRC[T/C]0 CLKREQ#A control 1 = SRC[T/C]0 stoppable by CLKREQ#A pin 0 = SRC[T/C]0 not controlled by CLKREQ#A pin Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm Crystal Recommendations Clock Chip The CY28441 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28441 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. See Table 5. Ci1 Ci2 Pin 3 to 6p Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Cs1 X1 X2 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Figure 1. Crystal Capacitive Clarification Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. = 1 ( Ce1 + Cs1 + Ci1 + 1 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) Rev 1.0, November 21, 2006 Page 8 of 19 CY28441 CLK_REQ[0:1]# Description The CLKREQ#[A:B] signals are active LOW input used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ#[A:B] are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it’s state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or de-assertion. (The assertion and deassertion of this signal is absolutely asynchronous.) . CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between 2-6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs will be driven HIGH within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater than 200 mV. CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ#[A:B] pins is all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ#[A:B] are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) – Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next HIGH to LOW transition and differential clocks must held HIGH or Hi-Zd (depending on the state of the control register drive mode bit) on the next diff clock# HIGH to LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tristate. Note Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100 and 133 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#. Rev 1.0, November 21, 2006 Page 9 of 19 CY28441 PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform Tstable 200mV short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Figure 7. CPU_STP# Deassertion Waveform 1.8mS CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven Rev 1.0, November 21, 2006 Page 11 of 19 CY28441 1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z PCI_STP# Assertion[1] The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. Tsu PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. (See Figure 11.) PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI_STP# Assertion Waveform Tsu Tdrive_SRC PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform Note: 1. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 55 and the other is SMBus byte6 bit 3. These two inputs are logically OR’ed. If either the external pin or the internal SMBus register bit is set LOW then the stoppable PCI clocks will be stopped in a logic LOW state. Rev 1.0, November 21, 2006 Page 12 of 19 CY28441 FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 0.2-0.3mS Delay State 1 W ait for VTT_PW RGD# Sample Sels State 2 State 3 Device is not affected, VTT_PW RGD# is ignored Clock Outputs Off On Clock VCO Off On Figure 12. VTT_PWRGD# Timing Diagram S1 S2 VTT_PWRGD# = Low Delay >0.25mS VDD_A = 2.0V Sample Inputs straps Wait for