CY28446LFXC

CY28446 Clock Generator for Intel Calistoga Chipset Features • Compliant to Intel® CK410M • Selectable CPU frequencies • Low power differential CPU clock pairs • 100 MHz Low power differential SRC clocks • 96 MHz Low power differential DOT clock • 48 MHz USB clock • SRC clocks stoppable through OE# Table 1. Output Configuration Table CPU x2/x3 SRC x9/10 PCI x5 REF x1 DOT96 x1 48M x1 • 33 MHz PCI clocks • Buffered 14.318 MHz reference clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V Power supply • 64 pin QFN package Pin Configuration FS_B/TEST_MODE VTTPWRGD#/PD FS_C/TEST_SEL PCIF0/ITP_EN USB_48/FS_A DOTC_96 DOTT_96 VDD_PCI VSS_PCI VSS_PCI VDD_48 OE1# PCI0 PCI1 PCI2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSS_48 SRCT0 SRCC0 OE0# SRCT1 SRCC1 OEA# SRCT2 SRCC2 VDD_SRC VSS_SRC OE3# SRCT3 SRCC3 OE6# PCI_STOP# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD_SRC SRCC5 SRCC6 SRCT5 SRCT6 SRCT8 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD_SRC VSS_SRC SRCC10 SRCT10 CPUC2_ITP/SRCC7 CPUT2_ITP/SRCT7 VDD_PCI REF VSS_REF XIN XOUT VDD_REF SDATA SCLK CPU_STOP# CPUT0 CPUC0 VSS_CPU VDD_CPU CPUT1 CPUC1 VSS_SRC CY28446 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SRCC8 OEB# SRCC9 SRCT9 Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 PCI3 Page 1 of 19 www.SpectraLinear.com CY28446 Table 2. Frequency Table FS_C MID 0 0 0 0 MID MID MID 1 1 1 FS_B 0 0 1 1 0 0 1 1 0 1 1 FS_A 1 1 1 0 0 0 0 1 x 0 1 Reserved Hi-Z REF/2 REF/2 100 Hi-Z REF/8 REF/8 33 Hi-Z REF/24 REF/24 14.318 Hi-Z REF REF 100 Hi-Z REF/8 REF/8 96 Hi-Z REF REF 48 CPU 100 133 166 200 SRC/SATA 100 100 100 100 PCIF/PCI 33 33 33 33 REF 14.318 14.318 14.318 14.318 LCD 100 100 100 100 DOT96 96 96 96 96 USB 48 48 48 48 Hi-Z REF REF Rev 1.0, November 20, 2006 Page 2 of 19 CY28446 Pin Description Pin No. 1 Name VSS_48 Type GND Ground for outputs. O, DIF 100 MHz Differential serial reference clocks Description 2, 3, 5, 6, 8, SRC(0:3, 5:6, 8:10) 9, 13, 14, 18, [T/C] 19, 20, 21, 22, 23, 25, 26, 27, 28 4, 7, 12, 15, 24, 64 10, 17, 29, 11, 30, 33 16 31, 32 OE[0, 1, 3, 6, A, B]# VDD_SRC VSS_SRC PCI_STP# I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) PWR 3.3V power supply for outputs. GND Ground for outputs. I, PU 3.3V LVTTL input for PCI_STP# Stops SRC and PCI clocks not set to free running in the SMBUS registers. CPU2_ITPT/SRCT7, O, DIF Selectable differential CPU clock/100 MHz Differential serial reference clock. CPU2_ITPC/SRCC7 Selectable via Pin 53 PCIF0/ITP_EN O, DIF Differential CPU clock outputs. PWR 3.3V power supply for outputs. GND Ground for outputs. I, PU 3.3V LVTTL input for CPU_STP# active LOW. I I/O, OD SMBus-compatible SCLOCK. SMBus-compatible SDATA. VDD_CPU VSS_CPU CPU_STP# SCLK SDATA VDD_REF XOUT XIN VSS_REF REF VDD_PCI PCIF0/ITP_EN 34, 35, 38, 39 CPUT/C[0:1] 36 37 40 41 42 43 44 45 46 47 48, 54 53 PWR 3.3V power supply for outputs. O, SE 14.318 MHz crystal output. I 14.318 MHz crystal input. GND Ground for outputs. O,SE Fixed 14.318 MHz clock output. PWR 3.3V power supply for outputs. O, SE 33 MHz clock output I/O, PD 33 MHz clock output (not stoppable by PCI_STOP#)/3.3V LVTTL input for selecting pins 31/32 (CPU2_ITP[T/C]/SRC7[T/C]) (sampled on the VTT_PWRGD# assertion). 0 (default): SRC7[T/C] 1: CPU2_ITP[T/C] GND Ground for outputs. I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, and all I/O configuration pins,. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). I, PD 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. I/O, PU Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. PWR 3.3V power supply for outputs. O, DIF Fixed 96 MHz clock output. I, PU 3.3V-tolerant input for CPU frequency selection Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 49, 50, 51, 52 PCI[0:3] 55, 59 56 VSS_PCI VTT_PWRGD#/PD 57 FS_C/TEST_SEL 58 60 61,62 63 USB_48/FS_A VDD_48 DOT_96[T/C] FS_B/TEST_MODE Rev 1.0, November 20, 2006 Page 3 of 19 CY28446 Frequency Select Pins (FS_A, FS_B, and FS_C) Apply the appropriate logic levels to FSA, FSB, and FSC before CK-PWRGD assertion to achieve host clock frequency selection. When the clock chip sampled HIGH on CK-PWRGD and indicates that VTT voltage is stable then FSA, FSB, and FSC input values are sampled. This process employs a one-shot functionality and once the CK-PWRGD sampled a valid HIGH, all other FSA, FSB, FSC and CK-PWRGD transitions are ignored except in test mode optional. Clock device register changes are made at system initialization if required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after complete byte has been transferred. For byte write and byte read operations, the system controller accesses individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up, making this interface Table 3. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'. Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Byte Count–8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1–8 bits Acknowledge from slave Data byte 2–8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N–8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Read = 1 Acknowledge from slave Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits Acknowledge Data bytes from slave/Acknowledge Data Byte N from slave–8 bits NOT Acknowledge Stop Block Read Protocol Description Rev 1.0, November 20, 2006 Page 4 of 19 CY28446 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Data byte–8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits Read Acknowledge from slave Data from slave–8 bits NOT Acknowledge Stop Byte Read Protocol Description Control Registers Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name Description CPU2_ITP[T/C]/SRC7[T/C] CPU2_ITP[T/C]/SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable Reserved Reserved SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 @Pup 1 1 1 1 1 1 1 Name PCIF0 DOT_96[T/C] USB_48 REF Reserved CPU[T/C]1 CPU[T/C]0 PCIF0 Output Enable 0 = Disable, 1 = Enable DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enable USB_48 Output Enable 0 = Disable, 1 = Enable REF Output Enable 0 = Disable, 1 = Enable Reserved CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable Description Rev 1.0, November 20, 2006 Page 5 of 19 CY28446 Byte 1: Control Register 1 Bit 0 @Pup 0 Name Description CPU PLL Spread Enable PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off 1 = Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks) Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name Reserved Reserved PCI3 PCI2 PCI1 PCI0 Reserved Reserved Reserved set to 1 Reserved set to 1 PCI3 Output Enable 0 = Disable, 1 = Enable PCI2 Output Enable 0 = Disable, 1 = Enable PCI1Output Enable 0 = Disable, 1 = Enable PCI0 Output Enable 0 = Disable, 1 = Enable Reserved set to 1 Reserved set to 1 Description Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC7 Reserved SRC5 Reserved Reserved SRC2 Reserved Reserved Description Allow control of SRC[T/C]7 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Reserved set to 0 Allow control of SRC[T/C]5 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Reserved set to 0 Reserved set to 0 Allow control of SRC[T/C]2 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Reserved set to 0 Reserved set to 0 Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 1 0 1 1 1 Name Reserved DOT96[T/C] Reserved Reserved PCIF0 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Reserved set to 1 DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state Reserved set to 0 Reserved set to 1 Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Description Rev 1.0, November 20, 2006 Page 6 of 19 CY28446 Byte 5: Control Register 5 Bit 7 6 @Pup 0 0 Name Reserved CPU[T/C]2 Reserved set to 0 CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted Description 5 0 CPU[T/C]1 4 0 CPU[T/C]0 3 2 1 0 0 0 0 0 SRC[T/C] CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 1 0 1 Name REF/N or Tri-state Select REF/N or Tri-state Select 1 = REF/N, 0 = Tri-state Test Mode Reserved REF Test Mode Control 1 = Ref/N or Tristate, 0 = Normal Operation Reserved set to 1 REF Output Drive Strength 0 = Low, 1 = High Description SW PCI_STP Function PCI and PCIF clock outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI and PCIF outputs are to free running stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI and PCIF outputs resumes in a synchronous manner with no short pulses. FS_C FS_B FS_A FSC Reflects the value of the FS_C pin sampled on power-up 0 = FSC was low during VTT_PWRGD# assertion FSB Reflects the value of the FS_B pin sampled on power-up 0 = FSB was low during VTT_PWRGD# assertion FSA Reflects the value of the FS_A pin sampled on power-up 0 = FSA was low during VTT_PWRGD# assertion 2 1 0 HW HW HW Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Rev 1.0, November 20, 2006 Page 7 of 19 CY28446 Byte 8: Control Register 7 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 0 0 0 0 Name Reserved SRC[T/C]10 SRC[T/C]9 SRC[T/C]8 Reserved SRC10 SRC9 SRC8 Reserved set to 0 SRC[T/C]10 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]9 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]8 Output Enable 0 = Disable (Tri-state), 1 = Enable Reserved set to 0 Allow control of SRC[T/C]10 with assertion of OEA# 0 = Free running, 1 = Stopped with OEA# Allow control of SRC[T/C]9 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Allow control of SRC[T/C]8 with assertion of OEA# 0 = Free running, 1 = Stopped with OEA# Description Byte 9: Control Register 8 Bit 7 6 5 4 3 2 1 0 . @Pup 0 0 0 0 0 1 1 1 Name PCI3 PCI2 PCI1 PCI0 PCIF0 Reserved Reserved Reserved 33-MHz Output drive strength 0 = Low, 1 = High 33-MHz Output drive strength 0 = Low, 1 = High 33-MHz Output drive strength 0 = Low, 1 = High 33-MHz Output drive strength 0 = Low, 1 = High 33-MHz Output drive strength 0 = Low, 1 = High Reserved set to 1 Reserved set to 1 Reserved set to 1 Description Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW . Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm The CY28446 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the CY28446 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. It is not true that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side Page 8 of 19 Rev 1.0, November 20, 2006 CY28446 is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. Clock Chip CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci1 Ci2 Pin 3 to 6p Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) OE# Description Cs1 X1 X2 Cs2 Trace 2.8 pF XTAL Ce1 Ce2 Trim 33 pF The OE# signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by OE[A,B]# are determined by the settings in register byte 3 and byte 8. OE[0,1,3,6]# controls SRC[0,1,3,6], respectively. The OE# signal is a debounced signal and its state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) OE# Assertion (OE# -> LOW) All differential stopped outputs resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2 and 6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven HIGH within 10 ns of OE# deassertion to a voltage er than 200 mV. OE# Deassertion (OE# -> HIGH) The impact of deasserting the OE# pins is that all SRC outputs that are set in the control registers to stoppable via deassertion of OE# are stopped after their next transition. The final state of all stopped SRC clocks is Low/low. Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) OE# SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. OE# Deassertion/Assertion Waveform Rev 1.0, November 20, 2006 Page 9 of 19 CY28446 PD (Power down) Clarification The CKPWRGD/PWRDWN# pin is a dual-function pin. During initial power-up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internal to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, all clocks need to be driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PD (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven HIGH and “Diff clock#” driven LOW. If the control register PD drive mode bit PD C P U T , 133M H z C P U C , 133M H z S R C T 100M H z S R C C 100M H z U S B , 48M H z D O T 96T D O T 96C corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are LOW. Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166 and 200 MHz. If PD mode has the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#. The 96_100_SSC follows the DOT waveform selected for 96 MHz and the SRC waveform in 100 MHz mode. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power-down will be driven HIGH in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. P C I, 3 3 M H z REF Figure 4. Power down Assertion Timing Waveform T stable 200 mV Figure 6. CPU_STP# Deassertion Waveform 1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven CPU_STP# CPUT CPUC Figure 8. CPU_STP# Assertion Waveform Rev 1.0, November 20, 2006 Page 11 of 19 CY28446 PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. 1.8mS DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI_STP# Assertion Waveform Tdrive_SRC Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform Rev 1.0, November 20, 2006 Page 12 of 19 CY28446 FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 0.2-0.3mS Delay State 1 W ait for VTT_PW RGD# Sample Sels State 2 State 3 Device is not affected, VTT_PW RGD# is ignored Clock Outputs Off On Clock VCO Off On Figure 12. VTT_PWRGD# Timing Diagram S1 S2 VTT_PWRGD# = Low Delay >0.25mS VDD_A = 2.0V Sample Inputs straps Wait for