CY28RS480ZXC

CY28RS480 Clock Generator for ATI Features • Supports AMD CPU • 200 MHz differential CPU clock pairs • 100 MHz differential SRC clocks • 48 MHz USB clock • 33 MHz PCI clock • 66 MHz HyperTransport clock CPU x2 SRC x8 HTT66 x1 PCI x1 REF x3 USB_48 x1 RS480 Chipset • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages Block Diagram XIN XOUT CPU_STP# CLKREQ[0:1]# Pin Configuration VDD_REF REF[0:2] XTAL OSC PLL1 PLL Ref Freq Divider Network VDD_CPU CPUT[0:1], CPUC[0:1], VDD_SRC SRCT[0:5],SRCC[0:5] VDD_SRCS SRCST[0:1],SRCSC[0:1] VDD_PCI PCI VDD_HTT HTT66 IREF PD VDD_48 MHz PLL2 USB_48 SDATA SCLK I2C Logic XIN XOUT VDD_48 USB_48 VSS_48 NC SCLK SDATA NC CLKREQ#0 CLKREQ#1 SRCT5 SRCC5 VDD_SRC VSS_SRC SRCT4 SRCC4 SRCT3 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_REF VSS_REF REF0 REF1 REF2 VDD_PCI PCI0 VSS_PCI VDD_HTT HTT66 VSS_HTT CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0 56 SSOP/TSSOP CY28RS480 Rev 1.0, November 22, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 14 www.SpectraLinear.com CY28RS480 Pin Description Pin No. 41,40,45,44 50 37 52, 53, 54 7 8 27, 28, 30, 29 12, 13, 16, 17, 18, 19, 22, 23, 24, 25, 34, 33 10,11 Name CPUT/C PCI0 IREF REF[2:0] SCLK SDATA SRCST/C[1:0] SRCT/C[5:0] Type O I 33 MHz clock output. A precision resistor attached to this pin is connected to the internal current reference. SMBus-compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in power-down. Description O, DIF Differential CPU clock outputs. AMD K8 buffer (200 Mhz). O, SE 14.318 MHz REF clock output. Intel Type-5 buffer. I,PU I/O,PU SMBus-compatible SDATA.This pin has an internal pull-up, but is tri-stated in power-down. O, DIF Differentials Selectable serial reference clock. Intel Type-X buffer. Includes overclock support through SMBUS O, DIF 100 MHz differential serial reference clock. Intel Type-X buffer. CLKREQ#[0:1] I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard PD specification. This pin has an internal pull-down. 0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled O, SE 48 MHz clock output. Intel Type-3A buffer. O, SE 66 MHz clock output. Intel Type-5 buffer. PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND I O 3.3V power supply for USB outputs 3.3V power supply for CPU outputs 3.3V power supply for PCI outputs 3.3V power supply for REF outputs 3.3V power supply for Hyper Transport outputs 3.3V power supply for SRC outputs 3.3V power supply for SRC outputs 3.3V power supply for SRCS outputs 3.3V Analog Power for PLLs Ground for USB outputs Ground for CPU outputs Ground for PCI outputs Ground for REF outputs Ground for SRC outputs Ground for SRC outputs Ground for SRCS outputs Ground for HyperTransport outputs Analog Ground 14.318-MHz Crystal Input 14.318-MHz Crystal Output No Connects 4 47 3 43 51 56 48 14, 21 35 32 39 5 42 49 55 15, 20, 26 36 31 46 38 1 2 6, 9 USB_48 HTT66 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_HTT VDD_SRC VDD_SRC1 VDD_SRCS VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSS_SRC1 VSS_SRCS VSS_HTT VSSA XIN XOUT NC Rev 1.0, November 22, 2006 Page 2 of 14 CY28RS480 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 (6:5) (4:0) Chip select address, set to ‘00’ to access device Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N – 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 Start Slave address – 7 bits Write Acknowledge from slave Description Bit 1 8:2 9 10 Start Slave address – 7 bits Write Acknowledge from slave Byte Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave – 8 bits NOT Acknowledge Block Read Protocol Description Rev 1.0, November 22, 2006 Page 3 of 14 CY28RS480 Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 18:11 19 27:20 28 29 Description Command Code – 8 bits Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Bit 18:11 19 20 27:21 28 29 37:30 38 39 Byte Read Protocol Description Command Code – 8 bits Acknowledge from slave Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge Stop Control Registers Byte 0:Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC [T/C]0 SRCS[T/C]1 SRCS[T/C]0 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name REF2 REF1 REF0 PCI0 USB_48 RESERVED CPU[T/C]1 CPU[T/C]0 REF2 Output Enable 0 = Disable, 1 = Enable REF1 Output Enable 0 = Disable, 1 = Enable REF0 Output Enable 0 = Disable, 1 = Enable PCI0 Output Enable 0 = Disable, 1 = Enable USB_48MHz Output Enable 0 = Disable, 1 = Enable RESERVED CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description Rev 1.0, November 22, 2006 Page 4 of 14 CY28RS480 Byte 2: Control Register 2 Bit 7 @Pup 1 Name CPUT/C SRCT/C USB_48 PCI Reserved Reserved CPU SRC Reserved Reserved Spread Spectrum Selection ‘0’ = –0.35% ‘1’ = –0.50% 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 33-MHz Output Drive Strength 0 = 2x, 1 = 1x Reserved Reserved CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved Reserved Description 6 5 4 3 2 1 0 1 1 0 1 0 1 1 Byte 3: Control Register 3 Bit 7 @Pup 1 Name CLKREQ# Description CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped CPU pd drive mode 0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state SRC pd drive mode 0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state Reserved Reserved Reserved Reserved HTT66 Output Drive Strength0 = High drive, 1 = Low drive. 6 5 4 3 2 1 0 0 1 0 1 1 1 1 CPU SRC Reserved Reserved Reserved Reserved HTT66 Byte 4: Control Register 4 Bit 7 @Pup 0 Name SRC[T/C]5 Description SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running HTT66 Output enable 0 = Disabled, 1 = Enabled 6 0 SRC[T/C]4 5 0 SRC[T/C]3 4 0 SRC[T/C]2 3 0 SRC[T/C]1 2 0 SRC[T/C]0 1 1 HTT66 Rev 1.0, November 22, 2006 Page 5 of 14 CY28RS480 Byte 4: Control Register 4 (continued) Bit 0 @Pup 1 Name Reserved Reserved Description Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C]5 Description SRC[T/C]5 CLKREQ#1 control 1 = SRC[T/C]5 stoppable by CLKREQ#1 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#1 control 1 = SRC[T/C]4 stoppable by CLKREQ#1 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#1 control 1 = SRC[T/C]3 stoppable by CLKREQ#1 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#1 control 1 = SRC[T/C]2 stoppable by CLKREQ#1 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running Reserved Reserved 6 0 SRC[T/C]4 5 0 SRC[T/C]3 4 0 SRC[T/C]2 3 0 SRC[T/C]1 2 0 SRC[T/C]0 1 0 0 0 Reserved Reserved Byte 6: Control Register 6 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 HW HW HW HW Name TEST_SEL TEST_MODE REF Reserved Reserved Reserved Reserved Reserved Description REF/N or Three-state Select 1 = REF/N Clock, 0 = Three-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation REF Output drive strength 0 = Low drive, 1 = High drive Reserved Reserved Reserved Reserved Reserved Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Rev 1.0, November 22, 2006 Page 6 of 14 CY28RS480 Table 4. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm Crystal Recommendations The CY28RS480 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS480 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci1 Ci2 Pin 3 to 6p Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. X1 X2 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Figure 1. Crystal Capacitive Clarification Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in = 1 ( Ce1 + Cs1 + Ci1 + 1 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) Rev 1.0, November 22, 2006 Page 7 of 14 CY28RS480 CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[0:1]# Deassertion [Low to High Transition] The impact of deasserting the CLKREQ#[1:0] pins is all DIF outputs that are set in the control registers to stoppable via assertion of CLKREQ#[1:0] are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to ‘0’, the final state of all stopped SRC signals is SRCT clock = High and SRCC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref,. When the control register CLKREQ# drive mode bit is programmed to ‘1’, the final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. CLK_REQ[0:1]# Assertion [High to Low Transition] All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the Assertion to active outputs is between 2–6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to ‘1’ three-state), the all stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] Assertion to a voltage greater than 200 mV. CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[0:1] Assertion/Deassertion Waveform Rev 1.0, November 22, 2006 Page 8 of 14 CY28RS480 Absolute Maximum Conditions Parameter VDD VDDA VIN TS TA TJ ESDHBM ØJC ØJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. –0.5 –0.5 –0.5 –65 0 – 2000 – – V–0 1 Max. 4.6 4.6 VDD+0.5 +150 70 150 – 20 60 Unit V V VDC °C °C °C V °C/W °C/W Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description 3.3V ± 5% Condition Min. 3.135 Max. 3.465 Unit V VDD_REF, 3.3V Operating Voltage VDD_CPU, VDD_PCI, VDD_SRC, VDD_SRC1, VDD_SRCS VDD_48 VILSMBUS VIHSMBUS VIL VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD IPDD IPDT Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power Down Supply Current Power Down Supply Current At max load and frequency PD asserted, Outputs driven PD asserted, Outputs Hi-Z Except pull-ups or pull-downs 0