CY28RS600ZXCT

CY28RS600 Clock Generator for ATI Features • Supports Intel CPU • Selectable CPU frequencies • Differential CPU clock pairs (30% over/10%under clocked) • 100 MHz differential ATI Graphics clocks (100% over/10% under clocked) • 100 MHz differential SRC clocks (10% over/under clocked) RS5XX, 6XX Chipsets • 48 MHz USB clock • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 64-pin TSSOP packages CPU x3 SRC x8 ATIG X4 REF x3 USB_48 x2 Block Diagram Pin Configuration VDD_REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS_REF FSA_REF0 FSB_REF1 FSC_REF2 RESET_IN# CPU_STOP# CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 CPUT2 CPUC2 VDDA VSSA VSSSRC SRCT0 SRCC0 VSS_SRC VDD_SRC ATIGT0 ATIGC0 ATIGT1 ATIGC1 VDD_ATIG VSS_ATIG ATIGT2 ATIGC2 ATIGT3 ATIGC3 CLKREQC# XIN XOUT 14.318MHz Crystal PLL Reference VDD REF[0:2] VDD_CPU CPUT[0:2] CPUC[0:2] XIN XOUT VDD48 USB48_0 USB48_1 VSS48 VTTPWRGD#/PD CPU PLL CLKREQ# [C:A] RESET_IN# FS[C:A] SRC PLL Divider SCLK SDATA CLKREQA# Divider VSS_SRC SRCT6 SRCC6 SRCT5 CY28RS600 VDD_ATIG ATIGT[0:3] ATIGC[0:3] SRCT7 SRCC7 VDD_SRC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SRC PLL Divider VDD_SRC SRCT[0:7] SRCC[0:7] SRCC5 SRCT4_SATAT SRCC4_SATAC VSS_SRC VDD_SRC SRCT3 Fixed PLL VTT_PWRGD#/PD SDATA SCLK I2C Logic Divider VDD48 USB48[1:0] SRCC3 SRCT2 SRCC2 VDD_SRC VSS_SRC SRCT1 SRCC1 CLKREQB# 64 TSSOP Rev 1.0, November 22, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 17 www.SpectraLinear.com CY28RS600 Pin Description Pin No. 1 2 3 4 5,6 7 8 Name VDD_REF XIN XOUT VDD_48 USB_48 [1:0] VSS_48 VTT_PWRGD#/PD Type PWR I O PWR GND I PD I I/O 3.3V power supply for REF, XTAL 14.318-MHz Crystal Input 14.318-MHz Crystal Output 3.3V power supply for USB outputs Ground for USB outputs 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, and FS_C inputs. After asserting VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting power-down (active HIGH) SMBus-compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in power-down. SMBus-compatible SDATA.This pin has an internal pull-up, but is tri-stated in power-down. Description O, SE 48-MHz clock output. Intel Type-3A buffer 9 10 11, 32, 33 SCLK SDATA CLKREQ#[A:C] I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard PU specification. This pin has an internal pull-up. 0 = selected SRC output is enabled. 1 = selected SRC output is disabled. O, DIF 100-MHz differential serial reference clock. Intel Type-SR buffer. (10% overclocking support through SMBUS) 12, 13, 16, 17, 18, 19, 20, 21, 24, 25, 26, 27, 30, 31, 46, 47 14, 23, 28, 44 15, 22, 29, 45 34, 35, 36, 37, 40, 41, 42, 43 39 38 48 49 50 51, 52, 53, 54, 57, 58 55 56 59 SRCT/C[7:0] VDD_SRC VSS_SRC ATIGT/C[3:0] PWR GND 3.3V power supply for SRC outputs Ground for SRC outputs O, DIF Differential Selectable serial reference clock. Intel Type-SR buffer. Includes 50% overclock support through SMBUS PWR GND GND GND PWR 3.3V power supply for ATIG outputs Ground for ATIG outputs Ground for SRC outputs Analog Ground 3.3V Analog Power for PLLs VDD_ATIG VSS_ATIG VSS_SRC VSSA VDDA CPUT/C[2:0] VSS_CPU VDD_CPU CPU_STP# O, DIF Differential CPU clock output. Intel Type-SR buffer. GND PWR I, PU Ground for CPU outputs 3.3V power supply for CPU outputs 3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned off two cycles after assertion of this pin 3.3V LVTTL Input (Negative Edge Triggered) When this pin is asserted LOW, all PLLs will transition to a safe default frequency. This may be the POR defaults or a safe value stored in SMBUS registers. 60 RESET_IN# I, PU 61 62 63 64 REF2/FSC REF1/FSB REF0/FSA VSS_REF I/O, SE 14.318-MHz REF clock output/CPU Frequency Select Intel Type-5 buffer. I/O, SE 14.318-MHz REF clock output/CPU Frequency Select Intel Type-5 buffer. I/O, SE, 14.318-MHz REF clock output/CPU Frequency Select Intel Type-5 buffer. PWR GND for REF, XTAL Rev 1.0, November 22, 2006 Page 2 of 17 CY28RS600 Table 1. Frequency Select Table (FS_A FS_B FS_C) FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100 MHz 133 MHz 166 MHz 200 MHz 266 MHz 333 MHz 400 MHz SRC 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz ATIG 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz RESERVED optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USB 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz Frequency Select Pins (FS_A, FS_B, FS_C) Apply the appropriate logic levels to FSA, FSB, and FSC inputs before CK-PWRGD assertion to achieve host clock frequency selection. When the clock chip sampled HIGH on CK-PWRGD and indicates that VTT voltage is stable then FSA, FSB, and FSC input values are sampled. This process employs a one-shot functionality and once the CK-PWRGD sampled a valid HIGH, all other FSA, FSB, FSC, and CK-PWRGD transitions are ignored except in test mode Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, Access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h) . Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is Table 2. Command Code Definition Bit 7 (6:5) (4:0) Chip select address, set to ‘00’ to access device Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Byte Count–8 bits Acknowledge from slave Data byte 1–8 bits Acknowledge from slave Data byte 2–8 bits Acknowledge from slave Data Byte/Slave Acknowledges Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Read = 1 Acknowledge from slave Byte Count from slave–8 bits Acknowledge Data byte 1 from slave – 8 bits Block Read Protocol Description Rev 1.0, November 22, 2006 Page 3 of 17 CY28RS600 Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit .... .... .... Description Data Byte N – 8 bits Acknowledge from slave Stop Bit 47 55:48 56 .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Data byte–8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits Read Acknowledge from slave Data from slave–8 bits NOT Acknowledge Stop Byte Read Protocol Description Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data Byte N from slave – 8 bits NOT Acknowledge Block Read Protocol Description Control Registers Byte 0: Output Enable Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SRC[T/C]7 SRC[T/C]6 SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC [T/C]0 SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description Rev 1.0, November 22, 2006 Page 4 of 17 CY28RS600 Byte 1: Output Enable Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name Reserved Reserved ATIG[T/C]3 ATIG[T/C]2 ATIG[T/C]1 ATIG[T/C]0 CPU[T/C]2 CPU[T/C]1 Reserved Reserved ATIG[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable ATIG[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable ATIG[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable ATIG[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description Byte 2: Output Enable Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Name CPU[T/C]0 USB_48_1 USB_48_0 REF_2 REF_1 REF_0 Reserved CPU Spread Enable CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable USB_48_1 Output Enable 0 = Disable (Hi-Z), 1 = Enable USB_48_0 Output Enable 0 = Disable (Hi-Z), 1 = Enable REF_2 Output Enable 0 = Disable (Hi-Z), 1 = Enable REF_1 Output Enable 0 = Disable (Hi-Z), 1 = Enable REF_0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Reserved CPU_PLL (PLL1) Spread Spectrum Enable 0= Spread Off, 1 = Spread On Description Byte 3: SW_FREQ Selection Register Bit 7 6 5 4 3 @Pup HW HW HW 1 0 Name FSC FSB FSA ATIG_OC_SEL1 ATIG_OC_SEL0 SEL1 0 1 X 2 1 0 0 1 0 FSEL_C FSEL_B FSEL_A SEL0 0 0 1 ATIG Output 111.33–167 MHz 100–125 MHz 167–256 MHz N 167–250 200–250 167–256 Description Read Only bit which reflects the value of pin 62 @ VTTPWRGD# assertion Read Only bit which reflects the value of pin 61 @ VTTPWRGD# assertion Read Only bit which reflects the value of pin 60@ VTTPWRGD# assertion SW Frequency Selection Bits Rev 1.0, November 22, 2006 Page 5 of 17 CY28RS600 Byte 4: Spread Spectrum Control Register Bit 7 6 @Pup 0 0 Name CPU_SS1 CPU_SS0 Description CPU (PLL1) Spread Spectrum Selection 00: –0.5% (peak to peak) 01: ±0.25% (peak to peak) 10: –1.0% (peak to peak) 11: ±0.5% (peak to peak) ATIG (PLL2) Spread Spectrum Selection 00: –0.5% (peak to peak) 01: –1.0% (peak to peak) ATIG_PLL (PLL2) Spread Spectrum Enable 0 = Spread Off, 1 = Spread On SRC_PLL (PLL3) Spread Spectrum Enable 0 = Spread Off, 1 = Spread On USB48 Output Drive Strength 0 = 1x, 1 = 2x Reserved REF Output Drive Strength 0 = 1X, 1 = 2x 5 0 ATIG_SS0 4 3 2 1 0 0 0 1 0 0 ATIG_SS_OFF SRC_SS_OFF USB48 Reserved REF Byte 5: System Configuration Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 1 0 Name Reserved CPU2 CPU1 CPU0 Reserved Reserved Reserved CLKREQA# Reserved Allow control of CPU2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# assertion Allow control of CPU1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# assertion Allow control of CPU0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# assertion Reserved Reserved Reserved CLKREQA# Controls SRC0 0 = Not controlled, 1 = Controlled Description Byte 6: Revision and Device ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Device ID Bit 3 Device ID Bit 2 Device ID Bit 1 Device ID Bit 0 Description Byte 7: Vendor ID Bit 7 6 5 4 @Pup 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Rev 1.0, November 22, 2006 Page 6 of 17 CY28RS600 Byte 7: Vendor ID (continued) Bit 3 2 1 0 @Pup 1 0 0 0 Name Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Byte 8: SRC PLL (PLL3) Overclocking Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC_N[7] SRC_N[6] SRC_N[5] SRC_N[4] SRC_N[3] SRC_N[2] SRC_N[1] SRC_N[0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] Description Byte 9: Clock Request Mapping Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 1 0 0 Name CLKREQC# CLKREQC# CLKREQC# CLKREQC# CLKREQB# CLKREQB# CLKREQB# CLKREQB# Description CLKREQC# Controls ATIG3 0 = Not controlled, 1 = Controlled CLKREQC# Controls ATIG2 0 = Not controlled, 1 = Controlled CLKREQC# Controls ATIG1 0 = Not controlled, 1 = Controlled CLKREQC# Controls ATIG0 0 = Not controlled, 1 = Controlled CLKREQB# Controls SRC7 0 = Not controlled, 1 = Controlled CLKREQB# Controls SRC6 0 = Not controlled, 1 = Controlled CLKREQB# Controls SRC5 0 = Not controlled, 1 = Controlled CLKREQB# Controls SRC4 0 = Not controlled, 1 = Controlled Byte 10: Dynamic Frequency Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 1 1 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved SMSW_SEL_Bypass SMSW_SEL Reserved Reserved Reserved Reserved Reserved Reserved Smooth switch on/off 0: on 1: off Smooth Switch Select 0: Select CPU_PLL (PLL1) 1: Select ATIG_PLL (PLL2) Description Rev 1.0, November 22, 2006 Page 7 of 17 CY28RS600 Byte 11: WDT System Register Bit 7 @Pup 0 Name Recovery_Frequency Description This bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: Use HW settings 1: Recovery N[8:0] Timer_SEL selects the WD reset function at SRESET pin when WD time out. 0 = Reset and Reload Recovery_Frequency 1 = Only Reset Time_Scale allows selection of WD time scale 0 = 294 ms 1 = 2.34 s WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when the system clears the WD_TIMER time stamp. Watchdog timer time stamp selection 000: Reserved (test mode) 001: 1 * Time_Scale 010: 2 * Time_Scale 011: 3 * Time_Scale 100: 4 * Time_Scale 101: 5 * Time_Scale 110: 6 * Time_Scale 111: 7 * Time_Scale Watchdog timer enable, when the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable, 1 = Enable 6 0 Timer_SEL 5 4 3 2 1 1 0 0 0 0 Time_Scale WD_Alarm WD_TIMER2 WD_TIMER1 WD_TIMER0 0 0 WD_EN Byte 12: CPU DAF Register1 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CPU_DAF_N[7] CPU_DAF_N[6] CPU_DAF_N[5] CPU_DAF_N[4] CPU_DAF_N[3] CPU_DAF_N[2] CPU_DAF_N[1] CPU_DAF_N[0] Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[D:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. Byte 13: CPU DAF Register2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CPU_DAF_N[8] CPU_DAF_M[6] CPU_DAF_M[5] CPU_DAF_M[4] CPU_DAF_M[3] CPU_DAF_M[2] CPU_DAF_M[1] CPU_DAF_M[0] Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[D:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. Rev 1.0, November 22, 2006 Page 8 of 17 CY28RS600 Byte 14: ATIG DAF Register1 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name ATIG_DAF_N[7] ATIG_DAF_N[6] ATIG_DAF_N[5] ATIG_DAF_N[4] ATIG_DAF_N[3] ATIG_DAF_N[2] ATIG_DAF_N[1] ATIG_DAF_N[0] Description If Prog_ATIG_EN is set, the values programmed in ATIG_DAF_N[8:0] will be used to determine the ATIG output frequency. Byte 15: WDT Recovery Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name RECOVERY_N[7] RECOVERY_N[6] RECOVERY_N[5] RECOVERY_N[4] RECOVERY_N[3] RECOVERY_N[2] RECOVERY_N[1] RECOVERY_N[0] Description Used when RESET_IN# is asserted or the Watch Dog timer times out. This will be the safe value or last known good frequency of the CPU. It is set by the user before engaging in any overclocking exercise. M values revert to those set by the FS[C:A] pins Byte 16: Overclocking Support Register Bit 7 6 @Pup 0 0 Name ATIG_N8 FS[C:A] ATIG DAF bit N8 FS_override 0 = Select operating frequency by FS[C:A] input pins 1 = Select operating frequency by FSEL[C:A] register values RESERVED Enables the setting of SRC_PLL (PLL3) N values via byte 8 0 = Disable, 1 = Enable Enables the setting of ATIG_PLL (PLL2) N values via byte 17 0 = Disable, 1 = Enable Enables the setting of CPU_PLL (PLL1) M and N values via byte 15 and 16 0 = Disable, 1 = Enable Description 5 4 3 2 1 0 0 0 0 0 0 0 RESERVED Prog_SRC_EN Prog_ATIG_EN Prog_CPU_EN Watchdog Autorecovery Watchdog Autorecovery Mode 0 = Disable (manual), 1 = Enable (Auto) Recovery_N8 CPU Safe recovery bit 8 for RESET_IN and Watchdog timer timeout. Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm Crystal Recommendations Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capac- itance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. It is not true that load capacitors are in Rev 1.0, November 22, 2006 Page 9 of 17 CY28RS600 parallel with the crystal and are approximately equal to the load capacitance of the crystal. . (lead frame, bond wires, etc.) CLK_REQ[A:C]# Description The CLKREQ#[A:C] signals are active LOW inputs used for clean stopping and starting selected SRC outputs. The CLKREQ# signal is a debounced signal, its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[A:C]# Assertion Figure 1. Crystal Capacitive Clarification The impact of asserting the CLKREQ#[A:C] pins is that all DIF outputs that are set in the control registers to stoppable via assertion of CLKREQ#[A:C] are to be stopped after their next transition. The final state of all stopped DIF signals is Tri-state; both SRCT clock and SRCC clock outputs are driven to Tri-state. CLK_REQ[A:C]# Deassertion All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the deassertion to active outputs is between 2 and 6 SRC clock periods with all SRC outputs resuming simultaneously. PD (Power down) Clarification Clock Chip Calculating Load Capacitors IIn addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. . Ci1 Ci2 Pin 3 to 6p Cs1 X1 X2 Cs2 Trace 2.8 pF The VTT_PWRGD#/PD pin is a dual-function pin. During initial power up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. PD (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must are tri-stated on the next diff clock# HIGH-to-LOW transition within four clock periods. Figure 3 and this description are applicable for all valid CPU frequencies. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#. PD Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down are driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of XTAL Ce1 Ce2 Trim 33 pF Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 ( Ce1 + Cs1 + Ci1 + 1 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs ............................................. Stray capacitance (terraced) Ci .......................................................... Internal capacitance Rev 1.0, November 22, 2006 Page 10 of 17 CY28RS600 each other. Figure 3 is an example showing the relationship of clocks coming up. PD CPUT, 133MHz CPUC, 133MHz ATIGT/SRCT 100MHz ATIGC/SRCC 100MHz USB, 48MHz PCI, 33 MHz REF Tstable 200 mV Figure 6. CPU_ST0P# Deassertion Waveform S1 S2 VTT_PWRGD# = Low Delay >0.25 ms VDD_A = 2.0V Sample Inputs straps Wait for