CY2SSTU877BVXI-43T

CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • 1 to 10 differential clock buffer (SSTL_18) • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): 40 ps • Very low output-to-output skew: 40 ps • Auto power-down feature when input is low • 1.8V operation • Fully JEDEC-compliant (JESD 82-8) • 52-ball BGA distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#). The input clocks (CK, CK#), the feedback clocks (FBIN, FBIN#), the LVCMOS (OE, OS), and the analog power input (AVDD) control the clock outputs. The PLL in the CY2SSTU877 clock driver uses the input clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CK, CK#) are logic low, the device will enter a low-power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low-power state where all outputs, the feedback, and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FBIN, FBIN#) and the input clock pair (CK, CK#) within the specified stabilization time tL. Functional Description The CY2SSTU877 is a high-performance, low-skew, low-jitter zero delay buffer designed to distribute differential clocks in high-speed applications. This phase-locked loop (PLL) clock buffer is designed for a VDD of 1.8V, an AVDD of 1.8V and SSTL18 differential data input and output levels. This device is a zero delay buffer that Block Diagram Pin Configuration 1 A B C D E F G H J K CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 52 BGA Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 8 www.SpectraLinear.com CY2SSTU877 Pin Description Pin No. G1 H1 E1, F1 E6, F6 H6, G6 AGND AVDD FB_INT, FB_INC FB_OUTT, FB_OUTC Name 1.8V analog supply Feedback differential clock input Feedback differential clock output Ground Output enable (ASYNC) for CLKT[0:9] and CLKC [0:9] Output Select (Tied to GND or VDDQ) 1.8V supply Buffered output of input clock, CLK Buffered output of input clock, CLK Description Ground for 1.8V analog supply CLK_INT, CLK_INC Differential clock input with a (10K–100K ) pull-down resistor B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, GND J5 F5 D5 D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 A2, A1, D1, J1, K3, A5, A6, D6, J6, K4, A3, B1, C1, K1, K2, A4, B6, C6, K6, K5 Table 1. Function Table Inputs AVDD GND GND GND GND VDD VDD VDD VDD VDD X OE H H L L L L H H X X OS X X H L H L X X X X CLK_INT CLK_INC L H L H L H L H L H H L H L H L H L L H OE OS VDDQ CLKT [0:9] CLKC [0:9] Outputs CLKT L H Lz Lz,CLKT7 Active Lz Lz,CLKT7 Active L H Lz CLKC H L Lz Lz,CLKC7 Active Lz Lz,CLKC7 Active H L Lz FB_OUTT FB_OUTC L H L H L H L H Lz Reserved H L H L H L H L Lz PLL Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off On On On On Off Recommended Operating Conditions Parameter TA (Com.) VDD, AVDD Description Ambient Operating Temp Operating Voltage Condition Min. 0 1.7 Max. 70 1.9 Unit °C V Rev 1.0, November 21, 2006 Page 2 of 8 CY2SSTU877 Absolute Maximum Conditions Parameter VIN VOUT TS VCC, AVCC IIK IOK IO Description Input Voltage Range Output Voltage Range Storage Temperature Supply Voltage Range Input Clamp Current Output Clamp Current Continuous Output Current Continuous Current through VDD/GND Condition Min. –0.5 –0.5 –65 –0.5 –50 –50 –50 –100 Max. VDDQ + 0.5 VDDQ + 0.5 150 2.5 50 50 50 100 Unit V V °C V mA mA mA mA DC Electrical Specifications Parameter VIK VOD VOX VIX VID DC VID AC VIL VIH VOL VOH IIH IIL IODL IDDLD IDD IOH IOL CIN COUT CIN(DELTA) Description Input Clamping Voltage Output Differential Voltage Output Differential Crossing Voltage Input Differential Crossing Voltage Input Differential Voltage (DC Values) Input Differential Voltage (AC Values) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Current Input Low Current Output disabled low current Static Supply current Dynamic Supply Current Output High Current Output Low Current Input Capacitance (Input Capacitance of CLK_INT, CLK_INC, FB_INT, FB_INC) VI = VDDQ or GND Ci(delta) (CLK_INT, CLK_INC, FB_INT, FB_INC) VI = VDDQ or GND 2 (OE, OS, CLK_INT, CLK_INC) (OE, OS, CLK_INT, CLK_INC) IOL = 100 A IOL = 9 mA IOH = –100 A IOH = –9 mA VIN = VDDQ or GND VIN = VDDQor GND VODL= 100 mV OE = GND IDDQ + IADD, CLK_INT = CLK_INC = GND CL = 0 @ 270 MHz VDDQ – 0.2 1.1 –250 –10 100 500 300 –9 9 3 250 10 0.65 * VDDQ 0.1 0.6 Conditions II = –18 mA 0.5 VDDQ/2 – 0.08 (VDDQ/2) – 0.15 0.3 0.6 VDDQ/2 + 0.08 (VDDQ/2) + 0.15 VDDQ + 0.4 VDDQ + 0.4 0.35 * VDDQ Min. Max. –1.2 Unit V V V V V V V V V V V V A A A A mA mA mA pF pF –0.25 0.25 pF Rev 1.0, November 21, 2006 Page 3 of 8 CY2SSTU877 AC Timing Specifications Parameter FCLK[1,2] TDC TODC TLOCK TOENB TODIS Tjitt (cc) Tjit (Period) Tjit (H-Period) T( ) T( )DYN TSKEW SLR(O) SLR(I) Description Clock Frequency (Max) Clock Frequency (Application) Input Duty Cycle Output Duty Cycle PLL Lock Time Output Enable Time Output Disable Time Cycle-to-cycle jitter Period jitter Half Period Cycle-to-cycle jitter Static Phase Offset Dynamic Phase Offset Clock Skew Output Slew Rate Input Slew Rate CLKT/ CLKC[0:9], FB_OUTT, FB_OUTC CLK_INT, CLK_INC, FB_INT, FB_INC OE Above 270 MHz Below 270 MHz Average 1000 cycles OE to any CLKT/ CLKC[0:9] OE to any CLKT/ CLKC[0:9] Conditions Room temp and nominal VDDQ Room temp and nominal VDDQ Min. 125 250 40 48 – – – –40 –30 –45 –60 –50 –40 – 1.5 1 0.5 Max. 500 500 60 52 15 8 8 40 30 45 60 50 40 40 4 4 Unit MHz MHz % % s ns ns ps ps ps ps ps ps ps V/ns V/ns V/ns Figure 1. Test Loads for Timing Measurement Notes: 1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). 2. Application clock frequency indicates a range over which the PLL must meet all timing requirements. Rev 1.0, November 21, 2006 Page 4 of 8 CY2SSTU877 - Figure 2. Cycle-to-cycle Jitter tjit(per) - Figure 3. Period Jitter - Figure 4. Half Period Jitter Rev 1.0, November 21, 2006 Page 5 of 8 CY2SSTU877 Figure 5. Static Phase Offset (Differential Probes) Figure 6. Dynamic Phase Offset (Differential Probes) Figure 7. Output Skew Rev 1.0, November 21, 2006 Page 6 of 8 CY2SSTU877 CLKT/CLKC CLKT CLKC Figure 8. Output Enable and Disable Times CLKT CLKC Figure 9. Input/Output Slew Rates CARD VIA R1 Bead AVDD 4.7 pF 1206 0.1 µF 0603 2200 pF 0603 VDDQ PLL GND CARD VIA AGND Figure 10. AVDD Filtering[3,4,5] Ordering Information Part Number Lead-free and ROHS Compliant CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 CY2SSTU877BVXI-32T CY2SSTU877BVXC-43 CY2SSTU877BVXC-43T CY2SSTU877BVXI-43 CY2SSTU877BVXI-43T 52-pin VFBGA for DDR400 52-pin VFBGA for DDR400 52-pin VFBGA for DDR533 52-pin VFBGA for DDR533 Commercial, 0 to 70 C Industrial, –40 to 85 C Commercial, 0 to 70 C Industrial, –40 to 85 C 52-pin VFBGA for DDR400 – Tape& Reel Commercial, 0 to 70 C 52-pin VFBGA for DDR400 – Tape& Reel Industrial, –40 to 85 C 52-pin VFBGA for DDR533 – Tape& Reel Commercial, 0 to 70 C 52-pin VFBGA for DDR533 – Tape& Reel Industrial, –40 to 85 C Package Type Product Flow Notes: 3. Place the 2200-pF capacitor close to the PLL. 4. Use a wide trace for the PLL analog power and ground. Connect PLL & Caps to AGND trace & connect trace to one GND via (farthest from PLL). 5. Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.9 ohm DC max, 600 ohms@100 MHz). Rev 1.0, November 21, 2006 Page 7 of 8 CY2SSTU877 Package Drawing and Dimensions TOP VIEW 52 VFBGA 4.5 × 7.0 × 1.0 MM BV52A BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(52X) A1 CORNER 1 A B C 0.65 D 7.00±0.10 7.00±0.10 5.85 E F G H J K 2 3 4 5 6 6 5 4 3 2 1 A B C D E F G 2.925 H J K A B 4.50±0.10 A 1.625 0.65 3.25 B 4.50±0.10 0.55 MAX. 0.25 C 0.21±0.05 0.15(4X) 0.15 C SEATING PLANE 0.26 MAX. C 1.00 MAX DIMENSION IN MM REFERENCE JEDEC MO-225 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 8 of 8