CY2SSTV16859ZIT

CY2SSTV16859 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 mA per JESD78, Class II • 64-pin TSSOP/JEDEC and 56-pin QFN package availability • JEDEC specification supported The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. The LVCMOS RESET# input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power up. In the DDR DIMM application, RESET# is completely asynchronous with respect to CLK# and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register is cleared and the outputs are driven low quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. Description This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations. All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input. All outputs are SSTL_2, Class II compatible. Block Diagram Pin Configuration RESET # CLK CLK # D1 D VREF C Q1B R Q1A To 12 Other Channels Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET # GND CLK # CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ CY2SSTV16859 Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 7 www.SpectraLinear.com CY2SSTV16859 Pin Configuration (continued) VDDQ VDDQ VDDQ Q10A Q11A Q12A Q13A GND VDD Q8A Q9A D13 D12 D11 Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 D10 D9 D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 D5 D4 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 VDD VDDQ VDDQ VDDQ Q7B Q6B Q5B Q4B Q3B Q2B Q1B D1 D2 56 QFN Package Pin Description Pin TSSOP 51 7,15,34,39,43,50,54,58,63 37,46,60 6,18,27,33,38,47,59,64 45 16,14,13,12,11,10,9,8,5,4,3,2,1 38 37,48 26,33,45 9,17,23,27,34,44,49,55 32 7,6,5,4,3,2,1,56,54,53,52,51,50 QFN RESET# GND VDD VDDQ VREF QA(1:13) QB(1:13) D(1:13) Disable Clocking and Reset Latch Ground Supply Voltage Supply Voltage, Quiet Reference Voltage for Data Inputs D(1:13) Data Outputs Data Outputs Data Inputs Name Description 32,31,30,29,28,25,24,23,22,21,20, 22,21,20,19,18,16,15,14,13,12 19,17 11,10,8 35,36,40,41,42,44,52,53,55,56,57, 24,25,28,29,30,31,39,40,41,42 61,62 43,46,47 48,49 Table 1. Function Table[1,2,3] INPUTS RESET# H H H L Notes: 1. H = High voltage level. 2. L = Low voltage level. 3. X = Don’t care. 35,36 CLK, CLK# Differential Clock Signals D3 OUTPUT CLK# D L H Q L H Q0 L CLK L or H X or floating L or H X or floating X X or floating Rev 1.0, November 21, 2006 Page 2 of 7 CY2SSTV16859 Absolute Maximum Conditions[4,5] Parameter VTERM[6] VTERM[7] TSTG IOUT IIK IOK Idd ISS Description Terminal Voltage with respect to VSS Terminal Voltage with respect to VSS Storage Temperature DC Output Current Continuous Clamp Current Continuous Clamp Current Continuous Current through each VDD, VDDQ or VSS VIVSS VOVDD Condition Min. –0.5 –0.5 –65° –50 –50 –50 –100 Max. 3.6 VDD + 0.5 150°C 50 50 50 100 Unit V V °C mA mA mA mA Recommended Operating Conditions[8] Parameter VDD VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VI(PP) IOH IOL TA Supply voltage Output supply voltage PC1600,PC2100,PC2700 PC3200 Reference voltage (VREF = VDDQ/2) Termination voltage Input voltage AC Data Input high-level voltage AC Data Input low-level voltage DC Data Input high-level voltage DC Data Input low-level voltage RESET# Input high-level voltage RESET# Input low-level voltage CLK, CLK# Common-mode input voltage range CLK, CLK# Peak-to-peak input voltage High-level output current Low-level output current Operating free-air temperature PC1600,PC2100,PC2700 PC3200 Description Min. 2.3 2.3 2.5 1.15 1.25 VREF – 40 mV 0 VREF + 310 mV – VREF + 150 mV – 1.7 – 0.97 360 – – 0 Typ. 2.5 2.5 2.6 1.25 1.3 VREF – – – – – – – – – – – – Max. 2.7 2.7 2.7 1.35 1.35 VREF + 40 mV VDD – VREF – 310 mV – VREF – 150 mV – 0.7 1.53 – –20 20 85 Typ.[9] – – – – – – – Unit V V V V V V V V V V V V V V mV mA mA °C DC Electrical Specifications Parameter VIK VOH VOL II IDD Description Clamp Voltage II = –18 mA High level output IOH = –100 µA voltage IOH = –16 mA Low level output IOL = 100 µA voltage IOL = 16 mA All Inputs Static Standby VI = VDD or VSS RESET# = VSS IO = 0 Condition VDD 2.3V 2.3 to 2.7V 2.3V 2.3 to 2.7V 2.3 2.7V 2.7V Min. – VDD – 0.2 1.95 – – – – Max. –1.2 – – 0.2 0.35 ±5 10 Unit V V V V V µA µA Static Operating RESET# = VDD, VI = VIH(AC) or VIL(AC) 2.7 – – 40.0 mA Notes: 4. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. Stresses greater than those listed under Absolute Maximum Conditions may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 6. VDD/VDDQ terminals. 7. All terminals except VDD. 8. The RESET# input of the device must be held at VDD or VSS to ensure proper device operation. 9. All typical values are measured at TAMB = 25°C Rev 1.0, November 21, 2006 Page 3 of 7 CY2SSTV16859 DC Electrical Specifications (continued) Parameter IDDD Description Condition VDD 2.7V Min. – Typ.[9] 30.0 Max. – Unit µA/ clock MHz µA/ clock MHz /data input RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0 Dynamic operating – clock CLK and CLK# switching 50% duty only cycle Dynamic operating – per each data input RESET# = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK# switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycles. IOH = –20 mA IOL = 20 mA 2.7 – 15.0 – rOH rOL rO( ) Ci Output high Output low 2.3 to 2.7V 2.3 to 2.7V 2.5V 2.5 2.5 2.5 7 7 – 2.5 2.5 2.5 – – – – – – 20 20 4 3.5 3.5 3.5 pF pF pF |rOH – rOL| each IO = 20 mA, TA = 25°C separate bit Data Inputs CLK and CLK# RESET# VI = VREF + 310 mV VICR = 1.25V, VI(PP) = 360 mV VI = VDD or VSS AC Electrical Specifications VDD = 2.5V± 0.2V Parameter fclock tw tact tinact tsu th Clock Frequency Pulse duration, CLK, CLK# high or low Differential inputs active time (data inputs must be held low after RESET# is taken high). Differential inputs inactive time (data and clock inputs must be held at valid levels (not floating) after RESET# is taken low). Set-up time, fast slew rate[10, 12] Set-up time, slow slew Hold time, slow slew rate[11, 12] Data after CLK , CLK# Hold time, fast slew rate[10, 12] rate[11, 12] Data before CLK , CLK# Description Min. – 2.0 – – 0.75 0.9 0.75 0.9 Max. 280 – 22 22 – – – – Unit MHz ns ns ns ns ns ns ns Table 2. Switching Characteristics Over Recommended Operating Conditions[13] Parameter fmax tPHL tPD RESET# CLK and CLK# Q Q 1.1 From (Input) To (Output) VDD = 2.5V ± 0.2V Min. 280 Max. – 5 2.8 MHz ns ns Unit Notes: 10. For data signal input slew rate V/ns. 11. For data signal input slew rate V/ns and V/ns. 12. CLK and CLK# signals input slew rates are 1 V/ns. 13. See test circuits and waveforms. TA = 0°C to +85°C. Rev 1.0, November 21, 2006 Page 4 of 7 CY2SSTV16859 Output Buffer Characteristics Table 3. Output Buffer Voltage vs. Current (V/I) Characteristics Pull-Down Voltage (V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Min. I(mA) 0 6 10 15 19 23 27 30 34 36 38 40 42 43 44 44 45 45 45 45 45 46 46 46 46 46 46 46 Max. I(mA) 0 13 25 38 49 60 71 81 91 100 108 115 123 130 137 144 150 158 165 172 179 185 191 196 201 206 211 216 Min. I(mA) –55 –55 –54 –54 –54 –54 –53 –53 –53 –52 –52 –52 –51 –50 –48 –46 –44 –40 –38 –35 –31 –28 –23 –19 –15 –10 –5 0 Pull-Up Max. I(mA) –162 –161 –160 –159 –157 –156 –154 –152 –149 –146 –143 –140 –137 –134 –130 –125 –120 –112 –104 –96 –83 –72 –60 –49 –38 –27 –15 0 Table 4. Output Buffer Slew-Rate Characteristics dV/dt Rise Fall Min. 0.85 V/ns 1.00 V/ns Max. 15.9 V/ns 18.9 V/ns Rev 1.0, November 21, 2006 Page 5 of 7 CY2SSTV16859 Parameter Measurement Information[14] VDD = 2.5V ± 0.2V Timing Diagrams V TT* LVCMOS RESET# Input V IH V IL tPHL Output V TT VOH VOL V DD /2 F rom O u tp ut U nde r T e st R L = 5 0 O hm T e st P oint C L = 3 0 pF Figure 1. Load Circuit[15] V I(PP) Timing Input tsu V ICR th V IH ** V IL *** Figure 4. Voltage Waveforms Propagation Delay Times tw Input V REF * V REF * V IH ** V IL *** Data Input V REF * V REF * Figure 5. Voltage Waveforms Pulse Duration[18,19] Figure 2. Voltage Waveforms Set-up and Hold Times VI(PP) Input tPLH Output VTT VICR VICR tPHL VTT VOH VOL LVCMOS RESET# Input tinact IDD VDD/2 VDD/2 tact 90% VDD 0V 10% IDDH IDDL Figure 3. Voltage Waveforms Propagation Delay Times[16, 17] Figure 6. Voltage Waveforms Enable and Disable Times Low- and High-level Enabling Ordering Information Part Number CY2SSTV16859ZC CY2SSTV16859ZCT CY2SSTV16859ZI CY2SSTV16859ZIT CY2SSTV16859LFC CY2SSTV16859LFCT CY2SSTV16859LFI CY2SSTV16859LFIT 64-pin TSSOP 64-pin TSSOP– Tape and Reel 64-pin TSSOP 64-pin TSSOP – Tape and Reel 56-pin QFN 56-pin QFN – Tape and Reel 56-pin QFN 56-pin QFN– Tape and Reel Package Type Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0° to 70°C Commercial, 0° to 70°C Industrial, –40° to 85°C Industrial, –40° to 85°C Notes: 14. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 50-ohm output slew rate = 1 V/ns ±20% (unless otherwise specified). 15. CL includes probe and jig capacitance. 16. the outputs are measured one at a time with one transition per measurement. 17. *VTT = VREF = VDDQ/2. 18. **VIH = VREF + 350 mV (AC voltage levels). 19. ***VIL = VREF - 350 mV (AC voltage levels). Rev 1.0, November 21, 2006 Page 6 of 7 CY2SSTV16859 Package Drawing and Dimension 64-lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64 56-Lead QFN 8 x 8 MM LF56A While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 7 of 7