CY2SSTV857LFXC-32T

CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Features • Operating frequency: 60 MHz to 230 MHz • Supports 400 MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power management control input • High-impedance outputs when input clock < 20 MHz • 2.6V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP and 40 QFN package • Industrial temperature of –40°C to 85°C • Conforms to JEDEC DDR specification Description The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV857-32 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs. Block Diagram 3 2 Pin Configuration VS S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VS S Y5 # Y5 VD D Q Y6 Y6 # VS S VS S Y7 # Y7 VD D Q PD# FB IN FB IN # VD D Q FB O U T # FB O U T VS S Y8 # Y8 VD D Q Y9 Y9 # VS S PD 37 AVDD 16 Test and Powerdown Logic 5 6 10 9 20 19 22 23 46 47 44 43 Y0 Y0# Y1 Y1# Y2 Y2# Y3 Y3# Y4 Y4# Y5 Y5# Y6 Y6# Y7 Y7# Y8 Y8# Y9 Y9# FBOUT FBOUT# Y0 # Y0 VD D Q Y1 Y1 # VS S VS S Y2 # Y2 VD D Q VD D Q CLK C LK# VD D Q AVD D AVS S VS S Y3 # Y3 VD D Q Y4 Y4 # VS S CY2SSTV857-32 CLK CLK# FBIN FBIN# 13 14 36 35 39 40 PLL 29 30 27 26 32 33 Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 8 www.SpectraLinear.com CY2SSTV857-32 40 QFN Package VDDQ VDDQ Y1# Y0# Y5# Y1 Y0 Y5 Y6 Y6# VSS Y2# Y2 VDDQ CLK CLK# VDDQ AVDD AVSS VSS 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 Y7# Y7 VDDQ PD# FBIN FBIN# VDDQ VDDQ FBOUT# FBOUT 40 QFN CY2SSTV857-32 27 26 25 24 23 22 10 11 12 13 14 15 16 17 18 19 20 21 Y3# Y4# Y9# Y4 Y9 Y8 y3 VDDQ Pin Description Pin # 48 TSSOP 13, 14 35 36 3, 5, 10, 20, 22 2, 6, 9, 19, 23 5,6 25 26 37,39,3,12,14 36,40,2,11,15 Pin # 40 QFN Pin Name CLK, CLK# FBIN# FBIN Y(0:4) Y#(0:4) Y(9:5) Y#(9:5) FBOUT I/O[1] I I I O O O O O Pin Description Differential Clock Input. Electrical Characteristics LV Differential Input Feedback Clock Input. Connect to FBOUT# for Differential Input accessing the PLL. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock Outputs. Clock Outputs. Clock Outputs. Clock Outputs. Feedback Clock Output. Connect to FBIN for Differential Outputs normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Power Down Input. When PD# is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled Hi-Z and the PLL is powered down. 2.6V Power Supply for Output Clock Buffers. 2.6V Nominal 2.6V Power Supply for PLL. When VDDA is at 2.6V Nominal GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. Common Ground. Analog Ground. 0.0V Ground 0.0V Analog Ground Differential Outputs Differential Outputs 27, 29, 39, 44, 46 17,19,29,32,34 26, 30, 40, 43, 47 16,20,30,31,35 32 21 33 22 FBOUT# O 37 27 PD# I 4, 11,12,15, 21, 28, 34, 38, 45 16 4,7,13,18,23,24, 28,33,38 8 VDDQ AVDD 1, 7, 8, 18, 24, 25, 1,10 31, 41, 42, 48 17 9 VSS AVSS Note: 1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin ( 66 MHz f > 66 MHz Test Mode only Min. –75 –100 1.5 1.5 – –50 Typ. – – 3.5 3.5 – – Max. 75 100 7.5 7.5 100 50 Unit ps ps ns ns ps ps Low-to-High Propagation Delay, CLK to Y High-to-Low Propagation Delay, CLK to Y Any Output to Any Output Skew[14] Phase Error[14] Ordering Information Part Number CY2SSTV857ZC–32 CY2SSTV857ZC–32T CY2SSTV857LFC–32[15] CY2SSTV857LFC–32T CY2SSTV857ZI–32 CY2SSTV857ZI–32T CY2SSTV857LFI–32[15] CY2SSTV857LFI–32T Lead-Free CY2SSTV857ZXC–32 CY2SSTV857ZXC–32T CY2SSTV857LFXC–32[15] CY2SSTV857LFXC–32T CY2SSTV857ZXI–32 CY2SSTV857ZXI–32T [15] [15] [15] Package Type 48-pin TSSOP 48-pin TSSOP–Tape and Reel 40-pin QFN 40-pin QFN–Tape and Reel 48-pin TSSOP 48-pin TSSOP–Tape and Reel 40-pin QFN 40-pin QFN–Tape and Reel 48-pin TSSOP 48-pin TSSOP–Tape and Reel 40-pin QFN 40-pin QFN–Tape and Reel 48-pin TSSOP 48-pin TSSOP–Tape and Reel Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Industrial, –40 to 85 C Industrial, –40 to 85 C Industrial, –40 to 85 C Industrial, –40 to 85 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Industrial, –40 to 85 C Industrial, –40 to 85 C 857-32 0327L11 *SWR# Marketing Part Number Date Code and Fab Location Lot Code Figure 7. Actual Marking on the Device Notes: 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120 /16 pF, as shown in Figure 5. 15. The ordering part number differs from the marking on the actual device. See Figure 7 for the actual marking on the device. Rev 1.0, November 21, 2006 Page 7 of 8 CY2SSTV857-32 Package Drawing and Dimension 48-lead (240-mil) TSSOP II Z4824 0.500[0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 25 48 12.395[0.488] 12.598[0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] SEATING PLANE 0°-8° 0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 40-lead QFN 6 x 6 MM LF40A TOP VIEW SIDE VIEW BOTTOM VIEW 0.08[0.003] A 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] N 1 0.60[0.024] DIA. 2 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. C 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018] 5.70[0.224] 5.80[0.228] 5.90[0.232] 6.10[0.240] 0.30[0.012] 0.50[0.020] (PAD SIZE VARY BY DEVICE TYPE) 0°-12° 0.50[0.020] 4.45[0.175] 4.55[0.179] 0.24[0.009] 0.60[0.024] (4X) C SEATING PLANE While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 8 of 8 4.45[0.175] 4.55[0.179] E-PAD