CYW311OXCT

W311 FTG for VIA™ Pro-266 DDR Chipset Features • Maximized EMI Suppression using Cypress’s Spread Spectrum Technology • System frequency synthesizer for VIA Pro-2000 • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when Watchdog Timer time-out • Capable of generate system RESET after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte read/write and block read/ write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength for CPU and PCI output clocks • Programmable output skew between CPU, AGP and PCI • Supports Intel® Celeron® and Pentium® III class processor • Three copies of CPU output • Nine copies of PCI output • One 48 MHz output for USB • One 24 MHz or 48 MHz output for SIO • Two buffered reference outputs • Three copies of APIC output • Supports frequencies up to 200MHz • SMBus Interface for programming • Power management control inputs • Available in 48-pin SSOP Key Specifications CPU Cycle-to-cycle Jitter: .......................................... 250 ps CPU to CPU Output Skew........................................... 175 ps PCI Cycle-to-cycle Jitter: ............................................. 500 ps PCI to PCI Output Skew:............................................. 500 ps Block Diagram Pin Configuration[1] Note: 1. Signals marked with * have internal pull-up resistors Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 18 www.SpectraLinear.com W311 Pin Definitions Pin Name RST# CPU1:3 Pin No. 32 39, 38, 35 Pin Type O (open drain) O I O Pin Description System Reset Output: Open-drain system reset output. CPU Clock Output: Frequency is set by the FS0:4 input or through serial input interface. The CPU1:3 outputs are gated by the CLK_STOP# input. CPU Output Control: 3.3V LVTTL-compatible input that stop CPU1:3. PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through serial input interface; see Table 5 for details. PCI1:8 outputs are gated by the PCI_STOP# input. PCI_STOP# Input: 3.3V LVTTL-compatible input that stops PCI1:8. Free-Running PCI Clock Output: Frequency is set by FS0:4 inputs or through serial input interface; see Table 5 for details. Frequency Selection Inputs: Selects CPU clock frequency as shown in Table 1. AGP Clock Output: This pin serves as the select strap to determine device operating frequency as described in Table 5. APIC Clock Output: APIC clock outputs. 48 MHz Output/Frequency Select 3: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 5. 24_48 MHz Output/Frequency Select 2: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 5. Reference Clock Output 1/Frequency Select 4: 3.3V 14.318 MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 5. Reference Clock Output 0: 3.3V 14.318 MHz output clock. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318 MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318 MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, PCI outputs, reference outputs, 48 MHz output, and 24-48 MHz output, connect to 3.3V supply. CPU_STOP# PCI1:8 34 10, 11, 13, 14, 16, 17, 18, 20 33 9 21, 22 23, 26, 27 45, 44, 42 6 PCI_STOP# PCI_F FS0:1 AGP0:2 APIC0:2 48MHz/FS3 O O I O O I/O 24_48MHz/ FS2 REF1/FS4 7 47 I/O I/O REF0 SCLK SDATA X1 48 28 29 3 O I I/O I X2 VDD_REF, VDD_48MHz, VDD_PCI, VDD_AGP, VDD_CORE VDD_CPU, VDD_APIC 41 1, 5,15, 24, 31 I P 41, 46, 37 P Power Connection: Power supply for APIC and CPU output buffers, connect to 2.5V. Rev 1.0, November 25, 2006 Page 2 of 18 W311 Serial Data Interface The W311 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the Table 1. Bit 7 6:0 Descriptions 0 = Block read or block write operation 1 = Byte/Word read or byte/word write operation Byte offset for byte/word read or write operation. For block read or write operations, these bits need to be set at ‘0000000’. controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word write and byte read operations, system controller can access individual indexed byte. The offset of the indexed byte is encoded in the command code. The definition for the command code is defined in Table 2. Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop Block Read Protocol Description Rev 1.0, November 25, 2006 Page 3 of 18 W311 Table 3. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte low – 8 bits Acknowledge from slave Data byte high –- 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Data byte low from slave – 8 bits Acknowledge Data byte high from slave – 8 bits NOT acknowledge Stop Word Read Protocol Description 19 20:27 28 29:36 37 38 19 20 21:27 28 29 30:37 38 39:46 47 48 Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Data byte from slave – 8 bits Not Acknowledge Stop Byte Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Rev 1.0, November 25, 2006 Page 4 of 18 W311 W311 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# – – – – – – – – Name Reserved SEL2 SEL1 SEL0 FS_Override SEL4 SEL3 Reserved Default 0 0 0 0 0 1 0 0 Reserved See Table 5 See Table 5 See Table 5 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings See Table 5 See Table 5 Reserved Description 2. All unused register bits (reserved and N/A) should be written to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Byte 1: Control Register 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# Name Reserved Spread Select2 Spread Select1 Spread Select0 Default 0 0 0 0 Reserved ‘000’ = Normal (spread off) ‘001’ = Test Mode ‘010’ = Reserved ‘011’ = Three-Stated ‘100’ = –0.5% ‘101’ = ± 0.5% ‘110’ = ± 0.25% ‘111’ = ± 0.38% (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Bit 3 Bit 2 Bit 1 Bit 0 Byte 2: Control Register 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 35 38 39 42 CPU3 CPU2 CPU1 APIC2 1 1 1 1 Pin# 20 18 17 16 14 13 11 10 PC8 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Name Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Rev 1.0, November 25, 2006 Page 5 of 18 W311 Byte 3: Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# -7 6 7 9 27 26 23 Name Reserved SEL_48MHz 48MHz 24_48MHz PCI_F AGP2 AGP1 AGP0 Default 0 0 1 1 1 1 1 1 Reserved 0 = Select 24 MHz as output 1 = Select 48 MHz as output (default). (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Byte 4: Watchdog Timer Register Bit Bit 7 Pin# Name PCI_Skew1 Default 0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the pre scaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scalar is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches to “0”, it will set the WD_To_STATUS bit and generate Reset if RST_EN_WD is enabled 0 = 150 ms 1 = 2.5 sec Description Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PCI_Skew0 WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 0 1 1 1 1 1 Byte 5: Control Register 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 6 7 44 45 47 48 Name 48Mhz_DRV 24_48MHz_DRV APIC1 APIC0 Reserved Reserved REF1 REF0 Default 1 1 1 1 0 0 1 1 Description 0 = Norm, 1 = High Drive 0 = Norm, 1 = High Drive (Active/Inactive) (Active/Inactive) Reserved Reserved (Active/Inactive) (Active/Inactive) Rev 1.0, November 25, 2006 Page 6 of 18 W311 Byte 6: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 1 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Byte 7: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 1 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Byte 8: Vendor ID and Revision ID Register (Read Only) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Default 0 0 0 0 1 0 0 0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Pin Description Rev 1.0, November 25, 2006 Page 7 of 18 W311 Byte 9: System Reset and Watchdog Timer Register Bit Bit 7 Bit 6 Name Reserved PCI_DRV Default 0 0 Reserved PCI clock output drive strength 0 = Normal 1 = High Drive Reserved This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) 0 = Stop and re-load Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: itself into a recovery frequency mode after a watchdog timer time-out occurs. Under recovery frequency mode, W311 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W311 from its recovery frequency mode by clearing the WD_EN bit. Reserved Pin Description Bit 5 Bit 4 Reserved RST_EN_WD 0 0 Bit 3 RST_EN_FC 0 Bit 2 WD_TO_STATU S WD_EN 0 Bit 1 0 Bit 0 Reserved 0 Byte 10: Skew Control Register Bit Bit 7 Bit 6 Bit 5 Name CPU_Skew2 CPU_Skew1 CPU_Skew0 Default 0 0 0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Reserved Reserved Reserved AGP skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Description Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved AGP_Skew1 AGP_Skew0 0 0 0 0 0 Rev 1.0, November 25, 2006 Page 8 of 18 W311 Byte 11: Recovery Frequency N - Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Default 0 0 0 0 0 0 0 0 Description If ROCV_FREQ_SEL is set, W311 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. W312 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W311 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Byte 12: Recovery Frequency M- Value Register Bit Bit 7 Name ROCV_FREQ_SEL Default 0 Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] If ROCV_FREQ_SEL is set, W311 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs.The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. W311 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0 0 0 0 0 0 0 0 Byte 13: Programmable Frequency Select N-Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Default 0 0 0 0 0 0 0 0 Pin Description If Prog_Freq_EN is set, W311 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. W311 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Rev 1.0, November 25, 2006 Page 9 of 18 W311 Byte 14: Programmable Frequency Select N-Value Register Bit Bit 7 Name Pro_Freq_EN Default 0 Description Programmable output frequencies enabled 0 = disabled 1 = enabled If Prog_Freq_EN is set, W311 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 0 0 0 0 0 0 0 Byte 15: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 16: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 17: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Default 0 0 0 0 0 0 0 0 Description Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Pin# Name Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Vendor test mode Default 0 0 0 0 0 0 0 0 Description Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Reserved. Write with ‘0’. Pin# 47 6 7 21 22 Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input Vendor test mode Vendor test mode Vendor test mode Default X X X X X 0 1 1 Reserved. Write with ‘0’ Reserved. Write with ‘1’ Reserved. Write with ‘1’ Description Latched FS[4:0] inputs. These bits are read only. Rev 1.0, November 25, 2006 Page 10 of 18 W311 Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 200.0 190.0 180.0 170.0 166.0 160.0 150.0 145.0 140.0 136.0 130.0 124.0 66.6 100.0 118.0 133.3 66.8 100.2 115.0 133.6 66.8 100.2 110.0 133.6 105.0 90.0 85.0 78.0 66.6 100.0 75.0 133.3 3V66 66.6 76.0 72.0 68.0 66.4 64.0 75.0 72.5 70.0 68.0 65.0 62.0 66.6 66.6 78.7 66.6 66.8 66.8 76.7 66.8 66.8 66.8 73.3 66.8 70.0 60.0 56.7 78.0 66.6 66.6 75.0 66.6 PCI 33.3 38.0 36.0 34.0 33.2 32.0 37.5 36.3 35.0 34.0 32.5 31.0 33.3 33.3 39.3 33.3 33.4 33.4 38.3 33.4 33.4 33.4 36.7 33.4 35.0 30.0 28.3 39.0 33.3 33.3 37.5 33.3 Output Frequency PLL Gear Constants (G) 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized inTable 7. Rev 1.0, November 25, 2006 Page 11 of 18 W311 Table 6. Register Summary Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = Disabled (default) 1 = Enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer timeout occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block write to update both registers within the same SMBus bus operation. 0 = Stop and reload Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Programmable output frequencies enabled 0 = Disabled (default) 1 = Enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. FS_Override CPU_FSEL_N, CPU_FSEL_M ROCV_FREQ_SEL ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] WD_EN Pro_Freq_EN Rev 1.0, November 25, 2006 Page 12 of 18 W311 Table 6. Register Summary (continued) Name FS_Override Description When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer timeout occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] 0 = 150 ms 1 = 2.5 sec This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 5. The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. Table 7 lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. CPU_FSEL_N, CPU_FSEL_M ROCV_FREQ_SEL WD_PRE_SCALER RST_EN_WD RST_EN_FC How to Program CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. Table 7. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 50 MHz–129 MHz 130 MHz–248 MHz Gear Constants 48.00741 48.00741 Fixed Value for M-Value Register 93 45 Range of N-Value Register for Different CPU Frequency 97–255 127–245 Rev 1.0, November 25, 2006 Page 13 of 18 W311 Absolute Maximum Ratings[2] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi. tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating –0.5 to +7.0 –65 to +150 –55 to +125 0 to +70 2 (min.) Unit V °C °C °C kV Parameter VDD, VIN TSTG TB TA ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% Parameter Supply Current IDD IDD Logic Inputs VIL VIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Input High Current[4] Current[4] IOL = 1 mA IOH = –1 mA CPUT[1:3] APIC[0:2] CPU1:3 PCI_F, PCI1:8 AGP0:2 APIC0:2 REF0:1 48-MHz 24-MHz IOH Output High Current CPU1:3 PCI_F, PCI1:8 AGP0:2 APIC0:1 48-MHz 24-MHz IOH = –1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.5V VOL = 1.25V VOH = 1.5V VOH = 1.5V VOH = 1.5V GND – 0.3 2.0 – – – 3.1 2.2 27 20.5 40 40 25 25 25 25 31 40 27 27 25 – – – – – – – 57 53 85 85 37 37 37 55 55 85 44 44 37 0.8 VDD + 0.3 –25 10 50 – – 97 139 140 140 76 76 76 97 139 140 94 94 76 V V µA µA mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA 3.3V Supply Current 2.5V Supply Current CPU [1:3]=133 MHz[3] – – 260 25 – – mA mA Description Test Condition Min. Typ. Max. Unit Clock Outputs Output Low Voltage Output High Voltage Output Low Voltage Output Low Current Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. All clock outputs loaded with 6" 60 transmission lines with 22-pF capacitors. 4. Inputs have internal pull-up resistors Rev 1.0, November 25, 2006 Page 14 of 18 W311 DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% (continued) Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[5] Load Capacitance, Imposed on External Crystal[6] X1 Input Capacitance[7] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDD = 3.3V – – – – – – 1.65 18 28 – – – – – – 5 6 7 V pF pF pF pF nH Description Test Condition Min. Typ. Max. Unit Pin Capacitance/Inductance AC Electrical Characteristics TA = 0°C to +70°C, VDD = 3.3V±5%, VDD = 2.5V±5%fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition /Comments Measured on rising edge at 1.25 Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V CPU = 66.6 MHz 15 5.2 5.0 1 1 45 – – – – – – – – 15.5 – – 4 4 55 250 CPU = 100 MHz 10 3.0 2.8 1 1 45 – – – – – – – – 10.5 – – 4 4 55 250 CPU = 133 MHz 7.5 1.87 1.67 1 1 45 – – – – – – – – 8.0 – – 4 4 55 250 ns ns ns V/ns V/ns % ps Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tSK fST Output Skew – – – – 175 3 – – – – 175 3 – – – – 175 3 ps ms Frequency Assumes full supply Stabilization from voltage reached within Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo – 20 – – 20 – – 20 – Notes: 5. X1 input threshold voltage (typical) is 3.3V/2 6. The W311 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Rev 1.0, November 25, 2006 Page 15 of 18 W311 PCI Clock Outputs (Lump Capacitance Test Load = 30 pF) Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. Min. 30 12 12 1 1 45 – – 1.5 – Typ. – – – – – – – – – – Max. – – – 4 4 55 500 500 4 3 Unit ns ns ns V/ns V/ns % ps ps ns ms Zo – 30 – AGP Clock Outputs (Lump Capacitance Test Load = 30 pF) Parameter tP tH tL tR tF tD tJC Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Description Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. Min. 15 5.25 5.05 1 1 45 – Typ. – – – – – – – Max. – – – 4 4 55 500 Unit ns ns ns V/ns V/ns % ps tSK fST Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance – – – – 250 3 ps ms Zo – 30 – APIC Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated from PCI divided by 2 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. PCI/2 2 2 55 3 Max. Unit MHz V/ns V/ns % ms Zo Rev 1.0, November 25, 2006 Page 16 of 18 W311 REF Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 0.5 0.5 45 – Min. Typ. 14.318 – – – – 2 2 55 3 Max. Unit MHz V/ns V/ns % ms Zo – 40 – 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 – 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 0.5 0.5 45 – Min. Typ. 48.008 +167 57/17 – – – – 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm Zo – 40 – 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 24 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 – 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 0.5 0.5 45 – Min. Typ. 24.004 +167 57/34 – – – – 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm Zo – 40 –a Rev 1.0, November 25, 2006 Page 17 of 18 W311 Ordering Information Ordering Code W311H W311HT Lead-free CYW311OXC CYW311OXCT 48-pin SSOP 48-pin SSOP - Tape and Reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C 48-pin SSOP 48-pin SSOP - Tape and Reel Package Type Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C Package Drawing and Dimension 48-Lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 25, 2006 Page 18 of 18