SC660EYB

SC660E SMBus System Clock Buffer for Mobile Applications Features • 10 output buffers for high clock fanout applications • Each output can be internally disabled for EMI and power consumption reduction. • Separate power supply for each group of 2 clock outputs for mixed voltage application. • < 250ps skew between output clocks. • 28-pin SSOP package for minimum board space • Single output Tristate pin for testability Product Description The device is a high fanout system clock distributor. Its primary application is to create the large quantity of clocks needed to support a wide range of clock loads that are referenced to a single existing clock. Loads of up to 30 pF are supported. Primary application of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduced by running a single reference clock trace to this device and then using it to regenerate the clock that drives shorter traces by using the SC660 to generate the clocks at the target devices EMI is therefore minimized and board real estate is saved. Block Diagram VDDB Pin Configuration SDRAM(0:1) SDRAM(2:3) SDRAM4 FIN SDRAM5 VDD SDATA SCLOCK OE I2C SDRAM(6:7) SDRAM(8:9) VDDB SDRAM0 SDRAM1 VSS VDDB SDRAM2 SDRAM3 VSS FIN VDDB SDRAM4 VSS VDD SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDB SDRAM9 SDRAM8 VSS VDDB SDRAM7 SDRAM6 VSS OE VDDB SDRAM5 VSS VSS SCLOCK Rev 1.0, December 06, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 5 www.SpectraLinear.com SC660E Pin Description Pin No. 9 2,3,6,7,11,18,22,23 ,26,27 20 Name FIN Sdram(0:9) OE PWR VddB I/O I O I Type PAD BUF1 PAD Description This pin is connected to the input reference clock. This clock must be in the range of 10.0 to 100.0 Mhz. Low skew output clocks. Buffer Output Enable pin. This pin is low it is used to place all output clocks (CLK1:10) in a tri state condition. This feature facilitates in production board level testing to be easily implemented for the clocks that this device produces. Has internal pull-up resistor. Serial Data for SMBus control interface. This pin receives data streams from the SMBus bus and outputs an acknowledge for valid data. Serial Clock for SMBus control interface. Ground pins for clock output buffers. These pins must be returned to the same potential to reduce output clock skew. Power for output clock buffers. Pin for device core logic. 14 Sdata Vdd I/O PAD 15 4, 8, 12, 16, 17, 21, 25 1, 5, 10, 19, 24, 28 13 Sclock Vss VddB Vdd Vdd I PWR PAD - - PWR PWR Maximum Ratings[1] Input Voltage Relative to VSS:................................VSS-0.3V Input Voltage Relative to VDDQ or AVDD: ........... VDD+0.3V Storage Temperature: ................................. -65 C to + 150 C Operating Temperature:.................................... 0 C to +85 C Maximum Power Supply: ................................................ 3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS