SL2305SI-1

SL2305 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features 10 to 140 MHz operating frequency range Low output clock jitter: 45 ps-typ cycle-to-cycle jitter Low output-to-output skew: 50 ps-typ Low product-to-product skew: 125 ps-typ 3.3 V power supply range Low power dissipation: 26 mA-max at 66 MHz 42 mA-max at 140 MHz One input drives 5 outputs organized as 4+1 SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 8-pin SOIC and TSSOP packages Available in Commercial and Industrial grades Description The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2305 is available with two (2) drive strength versions. The -1 is the standard-drive version and -1H is the highdrive version. The SL2305 high-drive version operates up to 140MHz and the standard drive version -1 operates up to 100. The SL2305 enter into Power-Down (PD) mode if the input at CLKIN is DC (0 to VDD). In this power-down state all five (5) outputs are tri-stated and the PLL is turned off leading to less than 12 A-max of power supply current draw. Applications Printers and MFPs Digital Copiers PCs and Work Stations DTV Routers, Switchers and Servers Digital Embeded Systems Benefits Up to five (5) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low jitter and skew Low power dissipation Low cost Block Diagram Rev 1.4, May 25, 2007 Page 1 of 11 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL2305 Pin Configuration 8-Pin SOIC or TSSOP Pin Description Pin Number 1 2 3 4 5 6 7 8 Pin Name CLKIN CLK2 CLK1 GND CLK3 VDD CLK4 CLKOUT Pin Type Input Output Output Power Output Power Output Output Pin Description Reference Frequency Clock Input. Weak pull-down (250k ). Buffered Clock Output Weak pull-down (250k ). Buffered Clock Output. Weak pull-down (250k ). Power Ground. Buffered Clock Output. Weak pull-down (250k ). 3.3V Power Supply. Buffered Clock Output. Weak pull-down (250k ). Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pulldown (250k ). Rev 1.4, May 25, 2007 Page 2 of 11 SL2305 General Description The SL2305 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. In addition to CLKOUT that is used for internal PLL feedback, there is a single bank with four (4) outputs, bringing the number of total available output clocks to five (5). Input and output Frequency Range The input and output frequency range is the same. But, the frequency range depends on the drive levels and load capacitance (CL) as given in the below Table 1. High and Low-Drive Product Options The SL2305 is offered with High-Drive “-1H” and StandardDrive “-1” options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve outputto-output and input-to-output skew specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of CLKOUT relative to the clock outputs since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL2305 is designed to operate from 3.0V (Min) to 3.6V (Max), complying with VDD=3.3V+/-10% requirement. An internal on-chip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Refer to SL23EP05 for 2.5V and SL23EPL05 for 1.8V power supply operation requirements. Temperature Range and Packages The SL2305 is offered with extended commercial temperature range of 0 to +70°C (C-Grade) and industrial temperature range of -40 to +85°C (I-Grade). The SL2305 is available in 8-pin SOIC (150-mil) and TSSOP (173-mil) packages. Drive HIGH HIGH STD STD CL(pF) 15 30 15 30 Min(MHz) 10 10 10 10 Max(MHz) 140 100 100 66 Table 1. Input/Output Frequency Range If the input clock frequency is DC (0 to VDD), this is detected by an input detection circuitry and all nine (5) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A-max supply current. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL2305 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its CLKIN (reference) input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency. Rev 1.4, May 25, 2007 Page 3 of 11 SL2305 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min – 0.5 – 0.5 0 – 40 – 65 – – 2000 Max 4.6 VDD+0.5 85 85 150 125 260 – Unit V V °C °C °C °C °C V Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol VDD TA Description 3.3V Supply Voltage Operating Temperature(Ambient) Load Capacitance 3.3V+/-10% Commercial Industrial Condition Min 3.0 0 –40 – – – – – 0.05 1.2 22 32 Max 3.6 85 85 15 30 15 30 7 100 Unit V °C °C pF pF pF pF pF ms MHz CLOAD 10 to 140 MHz, -1H high drive 10 to 100 MHz, -1H high drive 10 to 100MHz, -1 standard drive 10 to 66MHz, -1 standard drive CIN tpu CLBW ZOUT Input Capacitance Power-up Time Closed-loop bandwidth Output Impedance CLKIN pin Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). 3.3V, (typical) 3.3V (typical), -1H high drive 3.3V (typical), -1 standard drive Rev 1.4, May 25, 2007 Page 4 of 11 SL2305 DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol VDD VIL VIH IIL IIH VOL Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage (All outputs) Output HIGH Voltage (All outputs) Power Down Supply Current CLKIN=0 to VDD Condition Min 3.0 Max 3.6 0.8 VDD+0.3 25 50 0.4 0.4 – – 12 25 18 26 34 42 325 Unit V V V µA µA V V V V µA µA mA mA mA mA k CLKIN (Pin-1) CLKIN (Pin-1) CLKIN, 0 < VIN < 0.8V CLKIN, VIN = VDD IOL = 8 mA (standard drive) IOL = 12 mA (high drive) IOH = –8 mA (standard drive) IOH = –12 mA (high drive) C-Grade, Power-down if CLKIN=0 to VDD or input is floating I-Grade, Power-down if CLKIN=0 to VDD or input is floating – 2.0 – – – – 2.4 2.4 – – – – – – 175 VOH IDDPD IDD1 IDD2 IDD3 IDD4 RPD Power Supply Current Power Supply Current Power Supply Current Power Supply Current Pull-down Resistors All Outputs CL=0, 33-MHz CLKIN All Outputs CL=0, 66-MHz CLKIN All Outputs CL=0, 100-MHz CLKIN All Outputs CL=0, 140-MHz CLKIN Pins-1/2/3/5/7/8, 250k -typ Rev 1.4, May 25, 2007 Page 5 of 11 SL2305 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol FMAX1 Description Maximum Frequency (Input=Output ) All Active PLL Modes [1] Condition High drive (-1H). All outputs CL=15pF High drive (-1H), All outputs CL=30pF Standard drive, (-1), All outputs CL=15pf Standard drive, (-1), All outputs CL=30pf Min 10 10 10 10 30 40 – – – – – – Max 140 100 100 66 70 60 1.5 1.8 2.2 2.5 120 400 Unit MHz MHz MHz MHz % % ns ns ns ns ps ps INDC OUTDC tr/f Input Duty Cycle Output Duty Cycle [2] Measured at 1.4V, Fout=66MHz, CL=15pF Measured at 14V, Fout=66MHz, CL=15pF [2] Rise, Fall Time (3.3V) (Measured at: 0.8 to 2.0V) High drive (-1H), CL=10pF High drive (-1H), CL=30pF Standard drive (-1), CL=10pF Standard drive (-1), CL=30pF t1 t2 t3 Output-to-Output Skew (Measured at VDD/2) [2] All outputs CL=0 or equally loaded, -1 or -1H drives All outputs CL=0 or equally loaded, -1 or -1H drives Measured at VDD/2 Device-to-Device Skew (Measured at VDD/2) [2] Delay Time, CLKIN Rising Edge to CLKOUT Rising [2] Edge PLL Lock Time [2] –150 Time from 90% of VDD to valid clocks on all the output clocks 150 ps tPLOCK CCJ – – – – – 1.0 90 100 120 140 ms ps ps ps ps Cycle-to-cycle Jitter [2] Fin=Fout=66 MHz,