SL2309

SL2309 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features 10 to 140 MHz operating frequency range Low output clock skew: 50ps-typ Low output clock jitter: 50 ps-typ cycle-to-cycle jitter Low part-to-part output skew: 150 ps-typ 3.3 V power supply range Low power dissipation: 28 mA-max at 66 MHz 44 mA –max at 140 MHz One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades Description The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tristated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V. Applications Printers and MFPs Digital Copiers PCs and Work Stations DTV Routers, Switchers and Servers Digital Embeded Systems Benefits Up to nine (9) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram L ow Pow er and Low Jitter P LL C LKIN MUX CLK OU T CLK A1 CLK A2 C LKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 C LKB2 C LKB3 2 2 C LKB4 VD D GN D Rev 1.1, May 29, 2007 Page 1 of 12 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL2309 Pin Configuration 16-Pin SOIC and TSSOP Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name CLKIN CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 S1 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 CLKOUT Pin Type Input Output Output Power Power Output Output Input Input Output Output Power Power Output Output Output Pin Description Reference Frequency Clock Input. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). 3.3V Power Supply. Power Ground. Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Select Input, select pin S2. Weak pull-up (250k ). Select Input, select pin S1. Weak pull-up (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Power Ground. 3.3V Power Supply. Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250k ). Rev 1.1, May 29, 2007 Page 2 of 12 SL2309 General Description The SL2309 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and Output Frequency Range The input and output frequency range is the same. But, it depends on the drive and CL levels as given in the below Table 1. Drive HIGH HIGH LOW LOW CL(pF) 15 30 15 30 Min(MHz) 10 10 10 10 Max(MHz) 140 100 100 66 Select Input Control The SL2309 provides two (2) input select control pins called S1 (Pin-9) and S2 (Pin-8). This feature enables users to select various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k pull-up resistors to VDD. PLL Bypass Mode If the S1 and S2 pins are logic Low(0) and High(1) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks bank A, bank B and CLKOUT clocks are driven by directly from the reference input clock. In this operation mode SL2309 works like a non-ZDB fanout buffer. In this operation mode the input power-down detection circuit is disabled and outputs follow the input clock from DC to rated frequencies based on drive levels and load specifications. High and Low-Drive Product Options The SL2309 is offered with High Drive “-1H” and Standard Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI. Refer to the switching electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve the output-to-output skew and input-to-output specifications given in the switching electrical tables. However, Zero Delay between input and outputs can be adjusted by changing the loading at CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL2309 is designed to operate at VDD=3.3V (+/10%). An internal on-chip voltage regulator is used to provide PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Refer to SL23EP09 for 3.3V to 2.5V and SL23EPL09 for 1.8V power supply operations. weak Table 1. Input/Output Frequency Range If the input clock is DC (GND to VDD) or floating, this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A-max supply current. In PLL by-pass mode (S2=1 and S1=0), the detection circuit is disabled and input frequency range is 10 to 100MHz for standard (-1) drive and 10 to 140MHz for high (-1H) drive. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL2309 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Rev 1.1, May 29, 2007 Page 3 of 12 SL2309 S2 0 0 1 1 S1 0 1 0 1 Clock A1-A4 Tri-state Driven Driven Driven Clock B1-4 Tri-state Tri-state Driven Driven CLKOUT Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Status On On Off On Table 2. Select Input Decoding 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load – CLKA or CLKB Load (pF) Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) Rev 1.1, May 29, 2007 Page 4 of 12 SL2309 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min – 0.5 – 0.5 0 – 40 – 65 – – 2000 Max 4.6 VDD+0.5 85 85 150 125 260 – Unit V V °C °C °C °C °C V Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol VDD TA Description 3.3V Supply Voltage 3.3V+/-10% Condition Min 3.0 0 – 40 Max 3.6 85 85 Unit V °C °C Operating Temperature(Ambient) Commercial Industrial CLOAD Load Capacitance 10 to 140 MHz, -1H high drive All active PLL modes 10 to 100 MHz, -1H high drive All active PLL modes 10 to 100MHz, -1 standard drive All active PLL modes 10 to 66MHz, -1 standard drive All active PLL modes – 15 pF – 30 pF – 15 pF – 30 pF CIN tpu Input Capacitance Power-up Time S1, S2 and CLKIN pins Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). 3.3V, (typical) 3.3V, (typical), -1H high drive 3.3V, (typical), -1 standard drive – 0.05 7 100 pF ms CLBW ZOUT Closed-loop bandwidth Output Impedance 1.2 22 32 MHz Rev 1.1, May 29, 2007 Page 5 of 12 SL2309 DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol VDD VIL VIH IIL IIH VOL Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage (All outputs) Output HIGH Voltage (All outputs) CLKIN, S2 and S1 Pins CLKIN, S2 and S1 pins CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V CLKIN, S2 and S1 Pins, VIN = VDD IOL = 8 mA (standard drive) IOL = 12 mA (high drive) IOH = –8 mA (standard drive) IOH = –12 mA (high drive) Condition Min 3.0 – 2.0 – – – – 2.4 2.4 – – – – – – 175 Max 3.6 0.8 VDD+0.3 25 50 0.4 0.4 – – 12 25 20 28 36 44 325 Unit V V V µA µA V V V V µA µA mA mA mA mA k VOH IDDPD IDD1 IDD2 IDD3 IDD4 RPU/D Power Down Supply Current C-Grade CLKIN=0 to VDD or floating (input will be pulled-down by 250k I-Grade weak pull-down on-chip resistor) All Outputs CL=0, 33MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 66MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 100MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 140MHz CLKIN Power Supply Current S2=S1=1 (High) Pins-1/2/3/6/7/8/9/10/11/14/15/16 Pull-up and Pull-down Resistors 250k -typ Rev 1.1, May 29, 2007 Page 6 of 12 SL2309 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol FMAX1 Description Maximum Frequency (Input=Output ) All Active PLL Modes [1] Condition High drive (-1H). All outputs CL=15pF High drive (-1H), All outputs CL=30pF Standard drive, (-1), All outputs CL=15pf Standard drive, (-1), All outputs CL=30pf Min 10 10 10 10 0 0 0 0 30 40 – – – – – – 1.5 –150 – – – – – Typ – – – – – – – – 50 50 – – – – 50 150 5 – – 50 60 65 75 Max 140 100 100 66 140 100 100 66 70 60 1.5 1.8 2.2 2.5 120 400 8.7 150 1.0 100 120 130 150 Unit MHz MHz MHz MHz MHz MHz MHz MHz % % ns ns ns ns ps ps ns ps ms ps ps ps ps FMAX2 Maximum Frequency (Input=Output ) PLL Bypass Mode (S2=1 and S1=0) [1] High drive (-1H). All outputs CL=15pF High drive (-1H), All outputs CL=30pF Standard drive, (-1), All outputs CL=15pf Standard drive, (-1), All outputs CL=30pf INDC OUTDC tr/f Input Duty Cycle Output Duty Cycle [2] [2] Measured at 1.4V, Fout=66MHz, CL=15pF Measured at 1.4V, Fout=66MHz, CL=15pF High drive (-1H), CL=15pF High drive (-1H), CL=30pF Standard drive (-1), CL=15pF Standard drive (-1), CL=30pF Rise, Fall Time (3.3V) (Measured at: 0.8 to 2.0V) t1 t2 t3 Output-to-Output Skew (Measured at VDD/2) [2] All outputs CL=0 or equally loaded, -1 or -1H drives All outputs CL=0 or equally loaded, -1 or -1H drives PLL Bypass mode Only when S2=1 and S1=0 PLL enabled All active PLL modes Time from 90% of VDD to valid clocks on all the output clocks Device-to-Device Skew (Measured at VDD/2) [2] Delay Time, CLKIN Rising Edge to CLKOUT Rising [2] Edge (Measured at VDD/2) PLL Lock Time [2] tPLOCK CCJ Cycle-to-cycle Jitter [2] Fin=Fout=66 MHz,