SL23EP05SI-1

SL23EP05 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features 10 to 220 MHz operating frequency range Low output clock jitter: 20 ps-typ cycle-to-cycle jitter 15 ps-typ period jitter Low output-to-output skew: 30 ps-typ Low product-to-product skew: 60 ps-typ Wide 2.5 V to 3.3 V power supply range Low power dissipation: 16 mA-max at 66 MHz and VDD=3.3 V 14 mA-max at 66 MHz and VDD=2.5V One input drives 5 outputs organized as 4+1 SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 150 mil 8-pin SOIC package Available in Commercial and Industrial grades Description The SL23EP05 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP05 is available with two (2) drive strength versions called -1 and -1H. The -1 is the standard-drive version and -1H is the high-drive version. The SL23EP05 high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. The standard drive version -1 operates up to 167MHz and 133MHz at 3.3V and 2.5V respectively. The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is less then 2.0MHz or there is no rising edge. In this state all five (5) outputs are tri-stated and the PLL is turned off leading to less than 10 A of power supply current draw. Applications Printers and MFPs Digital Copiers PCs and Work Stations Routers, Switchers and Servers Digital Embeded Systems Benefits Up to five (5) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram Rev 1.0, May 21, 2007 Page 1 of 11 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL23EP05 Pin Configuration 8-Pin (150 mil) SOIC Pin Description Pin Number 1 2 3 4 5 6 7 8 Pin Name CLKIN CLK2 CLK1 GND CLK3 VDD CLK4 CLKOUT Pin Type Input Output Output Power Output Power Output Output Pin Description Reference Frequency Clock Input. Weak pull-down (150k ). Buffered Clock Output Weak pull-down (150k ). Buffered Clock Output. Weak pull-down (150k ). Power Ground. Buffered Clock Output. Weak pull-down (150k ). 3.3V or 2.5V Power Supply. Buffered Clock Output. Weak pull-down (150k ). Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pull-down (150k ). Rev 1.0, May 21, 2007 Page 2 of 11 SL23EP05 General Description High and Low-Drive Product Options The SL23EP05 is a low skew, low jitter Zero Delay Buffer with The SL23EP05 is offered with High-Drive “-1H” and Standardvery low operating current. Drive “-1” options. These drive options enable the users to The product includes an on-chip high performance PLL that control load levels, frequency range and EMI control. Refer to locks into the input reference clock and produces five (5) the AC electrical tables for the details. output clock drivers tracking the input reference clock for systems requiring clock distribution. Skew and Zero Delay In addition to CLKOUT that is used for internal PLL feedback, All outputs should drive the similar load to achieve output-tothere is a single bank with four (4) outputs, bringing the output skew and input-to-output specifications given in the AC number of total available output clocks to five (5). electrical tables. However, Zero delay between input and Input and output Frequency Range outputs can be adjusted by changing the loading of CLKOUT relative to the banks A and B clocks since CLKOUT is the The input and output frequency range is the same. But, it feedback to the PLL. depends on VDD and drive levels as given in the below Table 1. VDD(V) 3.3 3.3 2.5 2.5 Drive HIGH STD HIGH STD Min(MHz) Max(MHz) 10 10 10 10 220 167 200 133 Power Supply Range (VDD) The SL23EP05 is designed to operate in a wide power supply range from 2.250V (Min) to 3.360V (Max). This power supply range complies with 3.3V+/-10% and 2.5V+/-10% standard power supply requirements used in most systems. An internal on-chip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Contact SLI for 1.8V power supply version ZDB called SL23EPL05. Table 1. Input/Output Frequency Range If the input clock frequency is DC (0 to VDD), this is detected by an input frequency detection circuitry and all five (5) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 10 A supply current. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP05 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency. Rev 1.0, May 21, 2007 Page 3 of 11 SL23EP05 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min – 0.5 – 0.5 0 – 40 – 65 – – 2000 Max 4.6 VDD+0.5 85 85 150 125 260 – Unit V V °C °C °C °C °C V Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades Symbol Description VDD3.3 VDD2.5 TA 3.3V Supply Voltage 2.5V Supply Voltage Operating Temperature(Ambient) Commercial Industrial CLOAD Load Capacitance