SL23EP09SC-1

SL23EP09 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features 10 to 220 MHz operating frequency range Low output clock skew: 45ps-typ Low output clock jitter: 25 ps-typ cycle-to-cycle jitter 15 ps-typ period jitter Low part-to-part output skew: 90 ps-typ Wide 2.5 V to 3.3 V power supply range Low power dissipation: 26 mA-max at 66 MHz and VDD=3.3 V 24 mA-max at 66 MHz and VDD=2.5V One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades Description The SL23EP09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP09 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. Applications Printers, MFPs and Digital Copiers PCs and Work Stations Routers, Switchers and Servers Digital Embeded Systems Benefits Up to nine (9) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram L ow Pow er and Low Jitter P LL C LKIN MUX CLK OU T CLK A1 CLK A2 C LKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 C LKB2 C LKB3 2 2 C LKB4 VD D GN D Rev 1.1, February 2, 2007 Page 1 of 13 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL23EP09 Pin Configuration 16-Pin SOIC and TSSOP Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name CLKIN CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 S1 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 CLKOUT Pin Type Input Output Output Power Power Output Output Input Input Output Output Power Power Output Output Output Pin Description Reference Frequency Clock Input. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). 3.3V or 2.5V Power Supply. Power Ground. Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Select Input, select pin S2. Weak pull-up (250k ). Select Input, select pin S1. Weak pull-up (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Power Ground. 3.3V or 2.5V Power Supply. Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250k ). Rev 1.1, February 2, 2007 Page 2 of 13 SL23EP09 General Description The SL23EP09 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and output Frequency Range The input and output frequency range is the same. But, it depends on VDD and drive levels as given in the below Table 1. Select Input Control The SL23EP09 provides two (2) input select control pins called S1 and S2. This feature enables users to selects various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k pull-up resistors to VDD. PLL Bypass Mode If the S2 and S1 pins are logic High(1) and Low(0) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks bank A, bank B and CLKOUT clocks are driven directly from the reference input clock. In this operation mode SL23EP09 works like a non-ZDB fanout buffer. High and Low-Drive Product Options The SL23EP09 is offered with High-Drive “-1H” and Standard-Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve output-tooutput skew and input-to-output specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL23EP09 is designed to operate in a wide power supply range from 2.3V (Min) to 3.6V (Max). An internal onchip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Contact SLI for 1.8V power supply version ZDB called SL23EPL09. weak VDD(V) 3.3 3.3 2.5 2.5 Drive HIGH STD HIGH STD Min(MHz) 10 10 10 10 Max(MHz) 220 167 200 133 Table 1. Input/Output Frequency Range If the input clock frequency is DC (GND to VDD), this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A supply current. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP09 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Rev 1.1, February 2, 2007 Page 3 of 13 SL23EP09 S2 0 0 1 1 S1 0 1 0 1 Clock A1-A4 Tri-state Driven Driven Driven Clock B1-4 Tri-state Tri-state Driven Driven CLKOUT Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Status On On Off On Table 2. Select Input Decoding Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) Rev 1.1, February 2, 2007 Page 4 of 13 SL23EP09 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min. – 0.5 – 0.5 0 – 40 – 65 – – 2000 Max. 4.6 VDD+0.5 70 85 150 125 260 – Unit V V °C °C °C °C °C V Operating Conditions: Unless Otherwise Stated VDD=2.3V to 3.6V and for Both C and I Grades Symbol VDD3.3 VDD2.5 TA Description 3.3V Supply Voltage 2.5V Supply Voltage Operating Temperature(Ambient) 3.3V+/-10% 2.5V+/-10% Commercial Industrial Condition Min. 3.0 2.3 0 –40 – – – – – – – – 175 1.2 0.8 29 41 37 41 Max. 3.6 2.7 70 85 30 30 22 22 15 15 15 5 325 Unit V V °C °C pF pF pF pF pF pF pF pF k MHz MHz CLOAD Load Capacitance