W149

149 W149 440BX AGPset Spread Spectrum Frequency Synthesizer Features • Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Single chip system frequency synthesizer for Intel® 440BX AGPset • Two copies of CPU output • Six copies of PCI output • One 48 MHz output for USB • One 24 MHz output for SIO • Two buffered reference outputs • One IOAPIC output • Thirteen SDRAM outputs provide support for 3 DIMMs • Spread Spectrum feature always enabled • SMBus interface for programming • Power management control inputs • Smooth CPU frequency switching from 66.8–124 MHz Table 2. Pin Selectable Frequency Input Address FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 100 103 66.8 83.3 66.8 124 CPU0:1 (MHz) 100 PCI_F, 1:5 (MHz) 33.3 (CPU/3) (Reserved) 33.3 (CPU/3) 34.3 (CPU/3) 33.4 (CPU/2) 41.7 (CPU/2) 33.4 (CPU/2) 41.3 (CPU/3) ±0.5 –0.5 –0.5 –0.5 ±0.5 –0.5 Spread% –0.5 PCI to PCI Output Skew:............................................. 500 ps VDDQ3: ..................................................................... 3.3V±5% VDDQ2: ..................................................................... 2.5V±5% SDRAMIN to SDRAM0:12 Delay:.......................... 3.7 ns typ. Table 1. Mode Input Table[1] Mode 0 1 Pin 2 PCI_STOP# REF0 Key Specifications CPU Cycle-to-Cycle Jitter: ......................................... 250 ps CPU to CPU Output Skew: ........................................ 175 ps Logic Block Diagram VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC PLL Ref Freq Pin Configuration[2] REF1/FS2 VDDQ2 I/O Pin Control IOAPIC VDDQ2 CPU0 PLL 1 ÷2/÷3 CPU1 VDDQ3 PCI_F/MODE PCI1 PCI2 PCI3 PCI4 PCI5 Stop Clock Control VDDQ3 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI1 GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SMBus SDATA SCLK { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC REF1/FS2* GND CPU0 CPU1 VDDQ2 OE SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS0* 24MHz/FS1* W149 SDATA SCLK SMBus Logic PLL2 ÷2 VDDQ3 48MHz/FS0 SDRAMIN 24MHz/FS1 VDDQ3 SDRAM0:12 13 Notes: 1. Mode input latched at power-up. 2. Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 15 www.SpectraLinear.com W149 Pin Definitions Pin Name CPU0:1 PCI1:5 Pin No. 44, 43 8, 10, 11, 12, 13 7 Pin Type O O Pin Description CPU Clock Outputs: See Tables 2 and 6 for detailed frequency information. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: Frequency is set by the FS0:1 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. Upon power-up the mode input will be latched, which will determine the function of pin 2, REF0/(PCI_STOP#). See Table 1. Output Enable Input: When brought LOW, all outputs are placed in a high-impedance state. When brought HIGH, all clock outputs activate. IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up, FS0 input will be latched, which will set clock frequencies as described in Table 2. This output does not have the Spread Spectrum feature. 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be latched, which will set clock frequencies as described in Table 2. This output does not have the Spread Spectrum feature. I/O Dual-Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched which will set clock frequencies as described in Table 2. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function is determined by the MODE input. When set as an input, the PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply. Power Connection: Power supply for IOAPIC and CPU0:1 output buffers. Connect to 2.5V, or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. PCI_F/MODE I/O OE IOAPIC 48MHz/FS0 41 47 26 I O I/O 24MHz/FS1 25 I/O REF1/FS2 46 I/O REF0/ (PCI_STOP#) 2 I/O SDRAMIN SDRAM0:12 15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 24 23 4 I O SCLK SDATA X1 I I/O I X2 VDDQ3 5 1, 6, 14, 19, 27, 30, 36 42, 48 3, 9, 16, 22, 33, 39, 45 I P VDDQ2 GND P G Rev 1.0, November 21, 2006 Page 2 of 15 W149 Overview The W149 was developed as a single chip device to meet the clocking needs of the Intel 440BX AGPset. In addition to the typical outputs provided by standard 100-MHz 440BX AGPset FTGs, the W149 adds a thirteen output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. This feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. Upon W149 power-up, the first 2 ms of operation is used for input logic selection. During this period, the four I/O pins (7, 25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull each pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is