W320-03

W320-03 200 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Features • Compliant with Intel® CK-Titan Clock Synthesizer/Driver Specifications • Multiple output clocks at different frequencies • Three pairs of differential CPU outputs, up to 200 MHz • Ten synchronous PCI clocks, three free-running • Six 3V66 clocks • Two 48 MHz clocks • One reference clock at 14.318 MHz • One VCH clock • Spread Spectrum clocking (down spread) • Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) • Three Select inputs (Mode select & IC Frequency Select) • OE and Test Mode support • 56-pin SSOP package and 56-pin TSSOP package Benefits • Supports next-generation Pentium® processors using differential clock drivers • Motherboard clock generator • Support Multiple CPUs and a chipset • Support for PCI slots and chipset • Supports AGP, DRCG reference and Hub Link • Supports USB host controller and graphic controller • Supports ISA slots and I/O chip • Enables reduction of electromagnetic interference (EMI) and overall system cost • Enables ACPI-compliant designs • Supports up to four CPU clock frequencies • Enables ATE and “bed of nails” testing • Widely available, standard package enables lower cost Logic Block Diagram VDD_REF PWR Pin Configurations SSOP & TSSOP Top View VDD_REF XTAL_IN XTAL_OUT GND_REF PCI_F0 PWR Stop Clock Control X1 X2 XTAL OSC REF 1 2 3 4 5 6 7 8 9 10 11 56 55 54 53 52 51 50 49 48 47 46 REF S1 S0 CPU_STOP# CPU0 CPU#0 VDD_CPU CPU1 CPU#1 GND_CPU VDD_CPU CPU2 CPU#2 MULT0 IREF GND_IREF S2 USB DOT VDD_ 48 MHz GND_ 48 MHz 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA PLL Ref Freq PLL 1 S0:2 PWR_GD# CPU_STOP# Divider Network VDD_CPU CPU0:2 CPU#0:2 PCI_F1 PCI_F2 VDD_PCI GND_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI Gate PWR Stop Clock Control VDD_PCI PCI_F0:2 PCI0:6 W320-03 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI_STOP# /2 PWR_DWN# VDD_3V66 3V66_0 PWR PWR GND_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PWR_DWN# VDD_CORE GND_CORE PWR_GD# 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN PLL 2 VDD_48MHz PWR USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 SDATA SCLK SMBus Logic Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 16 www.SpectraLinear.com W320-03 Pin Summary Name REF XTAL_IN XTAL_OUT CPU, CPU# [0:2] 3V66_0 3V66_1/VCH 66IN/3V66_5 66BUFF [2:0] /3V66 [4:2] PCI_F [0:2] PCI [0:6] USB DOT S2 S1, S0 IREF MULT0 PWR_DWN# PCI_STOP# CPU_STOP# PWRGD# Pins 56 2 3 Description 3.3V 14.318 MHz clock output 14.318 MHz crystal input 14.318 MHz crystal input 44, 45, 48, 49, 51, Differential CPU clock outputs 52 33 35 24 21, 22, 23 5, 6, 7, 3.3V 66 MHz clock output 3.3V selectable through SMBus to be 66 MHz or 48 MHz 66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO 66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO 33 MHz clocks divided down from 66Input or divided down from 3V66 10, 11, 12, 13, 16, PCI clock outputs divided down from 66Input or divided down from 3V66 17, 18 39 38 40 54, 55 42 43 25 34 53 28 Fixed 48 MHz clock output Fixed 48 MHz clock output Special 3.3V 3 level input for Mode selection 3.3V LVTTL inputs for CPU frequency selection A precision resistor is attached to this pin which is connected to the internal current reference 3.3V LVTTL input for selecting the current multiplier for the CPU outputs 3.3V LVTTL input for Power_Down# (active LOW) 3.3V LVTTL input for PCI_STOP# (active LOW) 3.3V LVTTL input for CPU_STOP# (active LOW) 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SMBus compatible SDATA SMBus compatible Sclk SDATA SCLK 29 30 VDD_REF, VDD_PCI, 1, 8, 14, 19, 32, 46, 3.3V power supply for outputs VDD_3V66, 50 VDD_CPU VDD_48 MHz VDD_CORE 37 26 3.3V power supply for 48 MHz 3.3V power supply for PLL GND_REF, GND_PCI, 4, 9, 15, 20, 31, 36, Ground for outputs GND_3V66, 41, 47 GND_IREF, VDD_CPU GND_CORE 27 Ground for PLL Rev 1.0, November 25, 2006 Page 2 of 16 W320-03 Function Table S2 1 1 1 1 0 0 0 0 Mid Mid Mid Mid S1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 S0 [1] CPU (MHz) 66 MHz 100 MHz 200 MHz 133 MHz 66 MHz 100 MHz 200 MHz 133 MHz Hi-Z TCLK/2 Reserved Reserved 3V66[0:1] 66BUFF[0:2]/3 66IN/3V66_5 (MHz) V66[2:4] (MHz) (MHz) 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 Reserved Reserved 66 IN 66 IN 66 IN 66 IN 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 Reserved Reserved 66 MHz Input 66 MHz Input 66 MHz Input 66 MHz Input 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 Reserved Reserved PCI_F/PCI (MHz) 66 IN/2 66 IN/2 66 IN/2 66 IN/2 33 MHz 33 MHz 33 MHz 33 MHz Hi-Z TCLK/8 Reserved Reserved REF0(MHz) USB/DOT (MHz) Notes 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 1, 5 6, 7, 8 – – 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz Hi-Z TCLK Reserved Reserved Hi-Z TCLK/2 Reserved Reserved Swing Select Functions Mult0 0 1 Board Target Trace/Term Z 60 50 Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Output Current IOH = 4*IREF IOH = 6*IREF VOH @ Z 1.0V @ 50 0.7V @ 50 Clock Driver Impedances Impedance Minimum Buffer Name CPU, CPU# REF PCI, 3V66, 66BUFF USB DOT 3.135–3.465 3.135–3.465 3.135–3.465 3.135–3.465 VDD Range Buffer Type Type X1 Type 3 Type 5 Type 3A Type 3B 20 12 12 12 50 40 30 30 30 60 55 55 55 Typical Maximum Clock Enable Configuration PWR_DWN# CPU_STOP# PCI_STOP# 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 CPU IREF*2 IREF*2 IREF*2 ON ON CPU# FLOAT FLOAT FLOAT ON ON 3V66 LOW ON ON ON ON 66BUFF LOW ON ON ON ON PCI_F LOW ON ON ON ON PCI LOW OFF ON OFF ON USB/DOT LOW ON ON ON ON VCOS/ OSC OFF ON ON ON ON Notes: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. “Normal” mode of operation. 3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167PPM to match USB default. 5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V. 6. TCLK is a test clock over driven on the XTAL_IN input during test mode. 7. Required for DC output impedance verification. 8. These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock margining. Rev 1.0, November 25, 2006 Page 3 of 16 W320-03 Serial Data Interface (SMBus) To enhance the flexibility and function of the clock synthesizer, a two signal SMBus interface is provided according to the SMBus specification. Through the Serial Data Interface (SDI), various device functions such as individual clock output buffers, etc can be individually enabled or disabled. W320-03 support both block read and block write operations. The registers associated with the SDI initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a WRITE condition. The R/W bit is used by the SMBus controller as a data direction bit. A zero indicates a WRITE condition to the clock device. The slave receiver address is 11010010 (D2h). A command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. After the command code, the core logic issues a byte count which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. For example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count byte is required to be a minimum of one byte and a maximum of 32 bytes It may not be 0. Figure 1 shows an example of a block write. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. Start Slave Address R/W bit 1 1 0 1 0 0 1 0 0/1 1 bit 7 bits 1 A Command Code 00000000 8 bits A Byte Count = A Data Byte 0 A N 1 8 bits 1 8 bits 1 ... Data Byte N-1 A Stop bit 8 bits 1 1 bit 1 From Master to Slave From Slave to Master Figure 1. An Example of a Block Write Data Byte Configuration Map Data Byte 0: Control Register (0 = Enable, 1 = Disable) Bit Bit 7 Affected Pin# 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 – 35 44, 45, 48, 49, 51, 52 10, 11, 12, 13, 16, 17, 18 – – – Name PCI [0:6] CPU[2:0] 3V66[1:0] TBD 3V66_1/VCH CPU [2:0] CPU# [2:0] PCI [6:0] – – – Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On TBD VCH Select 66 MHz/48 MHz 0 = 66 MHz, 1 = 48 MHz CPU_STOP# Reflects the current value of the external CPU_STOP# pin PCI_STOP# (Does not affect PCI_F [2:0] pins) S2 Reflects the value of the S2 pin sampled on Power-up S1 Reflects the value of the S1 pin sampled on Power-up S0 Reflects the value of the S1 pin sampled on Power-up Type R/W Power On Default 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R R/W R R R 0 0 N/A N/A N/A N/A N/A Rev 1.0, November 25, 2006 Page 4 of 16 W320-03 Data Byte 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# – – 44, 45 48, 49 51, 52 44, 45 48, 49 51, 52 N/A N/A CPU2 CPU2# CPU1 CPU1# CPU0 CPU0# CPU2 CPU2# CPU1 CPU1# CPU0 CPU0# Name CPU Mult0 Value TBD Allow Control of CPU2 with assertion of CPU_STOP# 0 = Not free running; 1 = Free running Allow Control of CPU1 with assertion of CPU_STOP# 0 = Not free running;1 = Free running Allow Control of CPU0 with assertion of CPU_STOP# 0= Not free running; 1 = Free running CPU2 Output Enable 1 = Enabled; 0 = Disabled CPU1Output Enable 1 = Enabled; 0= Disabled CPU0 Output Enable 1 = Enabled; 0 = Disabled Description Type R R R/W R/W R/W R/W R/W R/W Power On Default N/A 0 0 0 0 1 1 1 Data Byte 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# – 18 17 16 13 12 11 10 N/A PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name N/A PCI6 Output Enable 1 = Enabled; 0 = Disabled PCI5 Output Enable 1 = Enabled; 0 = Disabled PCI4 Output Enable 1 = Enabled; 0 = Disabled PCI3 Output Enable 1 = Enabled; 0 = Disabled PCI2 Output Enable 1 = Enabled; 0 = Disabled PCI1 Output Enable 1 = Enabled; 0 = Disabled PCI0 Output Enable 1 = Enabled; 0 = Disabled Pin Description Type R R/W R/W R/W R/W R/W R/W R/W Power On Default 0 1 1 1 1 1 1 1 Data Byte 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 38 39 7 6 5 7 6 5 DOT USB PCI_F2 PCI_F1 PCI_F0 PCI_F2 PCI_F1 PCI_F0 Name Pin Description DOT 48-MHz Output Enable USB 48-MHz Output Enable Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# PCI_F2 Output Enable PCI_F1Output Enable PCI_F0 Output Enable Type R/W R/W R/W R/W R/W R/W R/W R/W Power On Default 1 1 0 0 0 1 1 1 Rev 1.0, November 25, 2006 Page 5 of 16 W320-03 Data Byte 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Pin# --33 35 24 TBD TBD 3V66_0 3V66_1/VCH 66IN/3V66_5 Name N/A N/A 3V66_0 Output Enable 1 = Enabled; 0 = Disabled 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled Pin Description Type R R R/W R/W Power On Default 0 0 1 1 1 R/W 3V66_5 Output Enable 1 = Enable; 0 = Disable NOTE: THIS BIT SHOULD BE USED WHEN PIN 24 IS CONFIGURED AS 3V66_5 OUTPUT. DO NOT CLEAR THIS BIT WHEN PIN 24 IS CONFIGURED AS 66IN INPUT. 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled R/W R/W R/W Bit 2 Bit 1 Bit 0 23 22 21 66BUFF2 66BUFF1 66BUFF0 1 1 1 Data Byte 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 6: Vendor ID Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description R R R R R R R R Type 0 0 0 1 0 1 0 0 Power On Default Pin# N/A N/A 66BUFF [2:0] 66BUFF [2:0] DOT DOT USB USB USB edge rate control DOT edge rate control Name N/A N/A Tpd 66IN to 66BUFF propagation delay control Pin Description Type R R R/W R/W R/W R/W R/W R/W Power On Default 0 0 0 0 0 0 0 0 Rev 1.0, November 25, 2006 Page 6 of 16 W320-03 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Input Voltage.............................................. –0.5V to VDD+0.5 Storage Temperature (Non-condensing)........................................–65 C to +150 C Max. Soldering Temperature (10 sec) ....................... +260 C Junction Temperature................................................ +150 C Package Power Dissipation............................................... 1 Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2000V Operating Conditions Over which Electrical Parameters are Guaranteed[9] Parameter VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_CPU, VDD_48 MHz TA Cin CXTAL CL Description 3.3V Supply Voltages 48-MHz Supply Voltage Operating Temperature, Ambient Input Pin Capacitance XTAL Pin Capacitance Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.85 0 Max. 3.465 3.465 70 5 22.5 20 30 14.318 MHz Unit V V C pF pF pF f(REF) Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads USB, REF, 3V66 PCI USB, REF, 3V66 PCI 0 < VIN < VDD 0 < VIN < VDD CPU For IOH =6*IRef Configuration REF, DOT, USB 3V66, DOT, PCI IOL Low-level Output Current REF, DOT, USB 3V66, PCI IOZ IDD3 Output Leakage Current Three-state Type X1, VOH = 0.65V Type X1, VOH = 0.74V Type 3, VOH = 1.00V Type 3, VOH = 3.135V Type 5, VOH = 1.00V Type 5, VOH = 3.135V Type 3, VOL = 1.95V Type 3, VOL = 0.4V Type 5, VOL =1.95 V Type 5, VOL = 0.4V 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 30 38 10 360 mA mA mA 29 27 –33 –33 mA –29 –23 IOH = –1 mA IOH = –1 mA IOL = 1 mA IOL = 1 mA –5 –5 12.9 14.9 2.4 2.4 0.4 0.55 5 5 Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V V V V mA mA mA IDDPD3 3.3V Shutdown Current VDD_CORE/VDD3.3 = 3.465V 20 Note: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Rev 1.0, November 25, 2006 Page 7 of 16 W320-03 Switching Characteristics[10] Over the Operating Range Parameter t1 t3 t3 t5 t5 t6 t7 t9 t9 t9 t9 t2 t3 t4 t8 Voh Vol Vcrossover t2 t3 t4 t8 All PCI,3V66 3V66[0:1] 66BUFF[0:2] PCI 3V66,PCI 3V66 USB, DOT PCI REF CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU Voh Vol Vcrossover CPU CPU CPU Output Description Output Duty Cycle[11] Falling Edge Rate 3V66-3V66 Skew 66BUFF-66BUFF Skew PCI-PCI Skew 3V66-PCI Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter RiseTime Fall Time CPU-CPU Skew Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage RiseTime Fall Time CPU-CPU Skew Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage Test Conditions Measured at 1.5V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.5V Measured at 1.5V Measured at 1.5V 3V66 leads. Measured at 1.5V Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured at 1.5V t9 = t9A – t9B Measured differential waveform from –0.35V to +0.35V Measured differential waveform from –0.35V to +0.35V Measured at Crossover Measured at Crossover t8 = t8A – t8B Measured with test loads[12] Measured with test loads[12] Measured with test loads[12] Measured with test loads[12] Measured single ended waveform from 0.175V to 0.525V Measured single ended waveform from 0.175V to 0.525V Measured at Crossover Measured at Crossover t8 = t8A – t8B With all outputs running Measured with test loads[13, 14] Measured with test loads [14] Min. 45 0.5 1.0 Max. 55 2.0 4.0 500 175 500 Unit % ps V/ns ps ps ps ns ps ps ps ps ps ps ps ps mV V V V ps ps ps ps % V V USB, REF, DOT Falling Edge Rate 1.5 3.5 250 350 500 1000 CPU 1.0V Switching Characteristics 175 175 467 467 150 150 325 0.92 –0.2 0.51 175 175 1.45 0.35 0.76 700 700 150 150 20 0.85 –0.15 0.28 0.43 CPU 0.7V Switching Characteristics Measured with test loads[14] Measured with test loads[14] V Notes: 10. All parameters specified with loaded outputs. 11. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 12. The 1.0V test load is shown on test circuit page. 13. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge. 14. The 0.7V test load is Rs = 33.2 , Rp = 49.9 in test circuit. Rev 1.0, November 25, 2006 Page 8 of 16 W320-03 Definition and Application of PWRGD# Signal Vtt VRM8.5 PWRGD# CPU BSEL0 BSEL1 3.3V 3.3V NPN 3.3V PWRGD# CLOCK GENERATOR S0 10K 10K GMCH S1 10K 10K Rev 1.0, November 25, 2006 Page 9 of 16 W320-03 Switching Waveforms Duty Cycle Timing (Single Ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD 0V t2 t3 OUTPUT CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 PCI-PCI Clock Skew PCI PCI t6 Rev 1.0, November 25, 2006 Page 10 of 16 W320-03 Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A Host_b Host t8B Cycle-Cycle Clock Jitter t9A t9B CLK PWRDWN# Assertion[15] 66BUFF PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF UNDEF Power Down Rest of Generator Note: 15. PCI_STOP# asserted LOW. Rev 1.0, November 25, 2006 Page 11 of 16 W320-03 PWRDWN# Deassertion[15] 10-30 s min. 100-200 s max.