SS6652CNTR

SS6652 Micro-Power Inverting DC/DC Controller n l l l l FEATURES 2.4V to 7V input voltage operation. Adjustable output voltage up to -40V. Low quiescent current at 80µA. Pulse frequency modulation maintains high efficiency (87%). 70KHz to 160KHz switching frequency. Power-saving shutdown mode (0.7µA typical). High efficiency with low cost external Pchannel MOSFET or PNP bipolar transistor. n DESCRIPTION The SS6652 is a high-performance inverting DC/DC controller, designed to drive an external power switch to generate programmable negative voltages, and is particularly suited to LCD bias contrast applications. Efficiency of 87% can be achieved with low cost PNP bipolar transistor drivers. Output voltage can be scaled to -40V or greater by two external resistors. A pulse frequency modulation scheme is employed to maintain high-efficiency conversion over a wide input voltage range. Quiescent current is about 80µA l l l n l APPLICATIONS Negative LCD Contrast Bias for 1. Notebook & Palmtop Computers. 2. Pen-Based Data System. 3. Portable Data Collection Terminals. 4. Personal Digital Assistants. and can be reduced to 0.7µA in shutdown mode. With switching frequencies in the 70KHz to 160KHz range, the small size switching components are ideal for battery powered portable equipment, like notebook and palmtop computers. l Negative Voltage Supply. n TYPICAL APPLICATION CIRCUIT VIN 2.4V ~ 7V RCL 100µF + C1 VIN VREF SHDN FB SS6652 0.047µF C4 R2 100K 10nF R1 1M C3 * Sumida CD-54 Series VOUT = -1.22V x R1/R2 CL DHI DLOW GND RB 470~1.8K 150µH *L 100µF C2 + Q1 9012 D1 1N5819 VOUT -12V~ -40V -10mA Negative LCD Contrast Bias Power Supply Rev.2.01 6/26/2003 www.SiliconStandard.com 1 of 6 SS6652 n ORDERING INFORMATION S S6652CXXX P ACKING TYPE TR: TAPE & REEL TB: TUBE PACKAGE TYPE N: PLASTIC DIP S: SMALL OUTLINE E X: SS6652CSTR à i n SO-8 Package in Tape & Reel Packing ( CN is not available in TR packing type.) PIN CONFIGURATION D IP-8 SO-8 TOP VIEW V IN VREF SHDN FB 1 2 3 4 8 7 6 5 CL DHI D LOW GND n ABSOLUTE MAXIMUM RATINGS Supply Voltage ..................................................................…………………............ 7V SHDN Voltage ...............................................……………..................................... 7V Operation Temperature Range ................................……….......................... 0°C~70°C Storage Temperature Range .................................…………................. -65°C~ 150°C n n TEST CIRCUIT Refer to Typical Application Circuit. ELECTRICAL CHARACTERISTICS PARAMETER Input Voltage Switch Off Current VREF Voltage VREF Source Current DLOW “ON Resistance” DHI “ON Resistance” CL Threshold Shutdown Threshold Shutdown Mode Current V SHDN = 0V (VIN=5V, Ta=25°C, unless otherwise specified.) MIN. 2.4 TYP. MAX. 7 80 1.16 250 5 7 70 0.8 1.5 0.7 2.4 2 1.22 150 1.28 UNIT V µA V µA Ω Ω mV V µA TEST CONDITIONS VFB=-50mV ISOURCE = 250µA Rev.2.01 6/26/2003 www.SiliconStandard.com 2 of 6 SS6652 n TYPICAL PERFORMANCE CHARACTERISTICS 350 300 1.5 250 Shutdown Current (µA) 2 3 4 5 6 7 8 Source Current (µA) 1 200 150 0.5 100 50 0 0 VIN (V) Fig. 1 VREF Source Current vs. VIN 1 2 3 4 5 6 7 8 Fig. 2 100 VIN (V) Shutdown Current vs. VIN 150 95 Frequency (KHz) 130 Duty Cycle (%) TA=0°C 90 110 TA=25°C TA=70°C TA=0°C 90 TA=25°C TA=70° C 4 85 70 50 2 3 80 VIN (V) 5 6 7 2 3 4 VIN (V) 5 6 7 Fig. 3 Frequency vs. VIN Voltage Fig. 4 Duty Cycle vs. VIN Voltage n BLOCK DIAGRAM VIN 1 CURRENT LIMIT COMPARATOR + PFM OSCILLATOR 1.22V REFERENCE VOLTAGE + V IN 70mV 8 CL V IN LATCH 7 DHI VREF 2 SHDN 3 OUTPUT DRIVER 6 DLOW 5 FB 4 - GND ERROR COMPARATOR Rev.2.01 6/26/2003 www.SiliconStandard.com 3 of 6 SS6652 n PIN DESCRIPTIONS PIN 1: VIN - Input supply voltage (2.4V~7V) PIN 2: VREF - Reference output (1.22V). Bypass with a 0.047µF capacitor to GND. Sourcing capability is guaranteed to be greater than 250µA. PIN 3: SHDN- Logic input to shutdown the chip. >1.5V = normal operation, GND = shutdown In shutdown mode DLOW and DHI pins are at high level. PIN 4: FB - Feedback signal input to sense ground. Connecting a resistor R1 to VOUT and a resistor R2 to VREF pin yields the output voltage: VOUT = - (R1/R2 ) x VREF PIN 5: GND - Power ground. PIN 6: DLOW - Driver sinking output. Connected to DHI when using an external Pchannel MOSFET. When using an external PNP bipolar transistor, connect a resistor RB from this pin to DHI. RB value depends on VIN, inductor and PNP bipolar transistor. By adjusting the RB value, efficiency can be optimized. PIN 7: DHI - Driver sourcing output. Connect to gate of the external P-channel MOSFET or base of the PNP bipolar transistor. - Current-limit input. This pin clamps the switch peak current to prevent over-current damage to the external switch. PIN 8: CL n APPLICATION INFORMATION The typical application circuit generates an adjustable Max. Output Power vs VIN 0.8 Typical Application Circuit 100µH 120µH 150µH 0.4 180µH 220µH Inductor Value 0.2 negative voltage for contrast bias of LCD displays. Efficiency and output power can be optimized by using appropriate inductor and switch. The following formulae provide a guideline for determining the optimal component values: L = (11.1 − 0.15 × V IN) × I OUT V IN × V OUT Max. Output Power (W) 0.6 PNP : 0 2 4 6 8 V CEO > V IN + V OUT I C, MAX ≥ 200 × I OUT VIN IOUT V IN V IN (V) V CE < 0. 4V at I C = 200 × and β = 10 RB ≅ 3 x L x (VIN - 0.8) where, VIN(V), VOUT(V), IOUT(A), L(µH), RB(Ω) Rev.2.01 6/26/2003 www.SiliconStandard.com 4 of 6 SS6652 n APPLICATION CIRCUIT (Refer to TYPICAL APPLICATION CIRCUIT) 90 90 VOUT = -15V L =150µH Efficiency (%) Efficiency (%) 85 VIN=5V VIN=3V VIN =7V 88 VOUT =-15V IOUT =-10mA L=220µH 86 80 84 L=150µH L=100µH 75 82 70 0 5 80 Load Current (mA) Fig. 5 Efficiency vs. Load Current 10 15 20 25 30 2 3 4 5 6 7 8 VIN (V) Fig. 6 Efficiency vs. VIN 90 90 VOUT =-22V L =120µH 85 Efficiency (%) Efficiency (%) VIN=5V VIN=3V VIN=7V 88 VOUT =-22V IOUT =-10mA L=220µH 86 80 L=150µH 84 75 82 L=100µH 70 0 5 10 15 20 25 30 80 2 3 4 5 6 7 8 Load Current (mA) Fig. 7 Efficiency vs. Load Current VIN (V) Fig. 8 Efficiency vs. VIN 90 90 VOUT =-30V L =100µH 85 VIN=7V 88 VOUT =-30V IOUT =-10mA L=150µH Efficiency (%) Efficiency (%) VIN=5V 80 86 L=120µH VIN=3V 84 75 82 L=100µH 70 0 5 Load Current (mA) Fig. 9 Efficiency vs. Load Current 10 15 20 25 30 80 2 3 4 5 6 7 8 VIN (V) Fig. 10 Efficiency vs. VIN Rev.2.01 6/26/2003 www.SiliconStandard.com 5 of 6 SS6652 n PHYSICAL DIMENSIONS l 8 LEAD PLASTIC SO (unit: mm) D SYMBOL A A1 H E MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 1.27 B C D E e A C A1 e H L L 1.27(TYP) B l 8 LEAD PLASTIC DIP (unit: mm) D SYMBOL A1 E1 MIN 0.381 2.92 0.35 0.20 9.01 7.62 6.09 — 2.92 MAX — 4.96 0.56 0.36 10.16 8.26 7.12 10.92 3.81 A2 b C E D E E1 C A2 A1 L e eB 2.54 (TYP) b e eB L Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.01 6/26/2003 www.SiliconStandard.com 6 of 6