SS6802AGSTB

SS6802 TWO-CELL LITHIUM-ION BATTERY PROTECTION IC FEATURES Ultra-Low Quiescent Current at 10µA (VCC=7V, VC=3.5V). Ultra-Low Power-Down Current at 0.2µA (VCC =3.8V, VC=1.9V). Wide Supply Range: 2 to 18V. Precision Overcharge Protection Voltage 4.35V ± 30mV for the SS6802A 4.30V ± 30mV for the SS6802B 4.25V ± 30mV for the SS6802C Built-in Delay Circuits for Overcharge, Over-discharge and Overcurrent Protection. Overcharge and Overdischarge Delay Time can be Extended by External Capacitors. Built-in Cell-balancing Bleeding Network under Overcharge Condition. DESCRIPTION The SS6802 battery protection IC is designed to protect lithium-ion batteries from damage due to overcharging, overdischarging, and overcurrent for two series cells in portable phones and laptop computers. It can be a part of the low-cost charge control system within a two-cell lithium-ion battery pack. Safe and full utilization charging is ensured by the accurate ±30mV overcharge detection. Three different specification values for overcharge protection voltage are provided for various protection requirements. The very low standby current drains little current from the cells while in storage. APPLICATIONS Protection IC for Two-Cell Lithium-Ion Battery Pack. Pb-free; RoHS-compliant TYPICAL APPLICATION CIRCUIT VBAT+ **R1 C1 1µF C2 1µF **R2 M1 CEM9926 2 OD SS6802 CS 7 8 5 *CTC 6 VC TD 3 *CTD 4 GND OC 1 R3 1M Q1 R6 1K M2 CEM9926 VCC TC BATTERY 1 BATTERY 2 R4 1M R5 C3 0.01µF 1M VBAT - *CTC & CTD are optional for delay time adjustment. **R1 & R2: Refer application informations. Protection Circuit for Two-Cell Lithium-Ion Battery Pack 02/26/2008 Rev.1.00 www.SiliconStandard.com 1 SS6802 ORDERING INFORMATION SS6802XXXXX PACKING TYPE TR: TAPE & REEL TB: TUBE PACKAGE TYPE S: SOP-8 G: LEAD FREE COMMERCIAL OVERCHARGE PROTECTION Example: SS6802AGSTR VOLTAGE 4.35V version, in A: 4.35V B: 4.30V SO-8 Lead Free C: 4.25V Package & Tape & Reel Packing Type PIN CONFIGURATION TOP VIEW OC OD TD GND 1 2 3 4 8 7 6 5 VCC CS VC TC ABSOLUTE MAXIMUM RATINGS Supply Voltage ....................................……………..................................................... 18V 5V DC Voltage Applied on VC, CS, OC, OD Pins ...............…………….............................. 18V DC Voltage Applied on TC, TD Pins ...............…………………..…….............................. Operating Temperature Range .......................................….………….............. -40°C~85°C Storage Temperature Range .........................…………………..................... - 65°C~150°C Junction Temperature .........................…………………...................………………… 125°C Lead Temperature (Soldering 10s) .........................…………………...................…. 260°C Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient (Assume no ambient airflow, no heatsink) Absolute Maximum Rating are those value beyond which the life of a device may be impaired. SOP-8 .........................……………… 40°C/W SOP-8 .........................…………… 160°C/W TEST CIRCUIT ICO 1 2 OC VCC 8 ICC VCC VCS VOD OD CS 7 VC 6 TC 5 3 TD 4 GND + CTD SS6802 IC VC + CTC 02/26/2008 Rev.1.00 www.SiliconStandard.com 2 SS6802 ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified.) PARAMETER Supply Current in Normal Mode Supply Current in Power-Down Mode VC Pin Input Current TEST CONDITIONS SYMBOL VCC=7V, VC=3.5V VCC=4.8V, VC=2.4V VCC=7V, VC=3.5V AIC1802A ICC IPD IC MIN. TYP. 10 0.8 400 MAX. 15 1.2 600 4.38 4.33 4.28 4.15 2.55 3.15 165 38 UNIT µA µA nA 4.32 VOCP 4.27 4.22 VOCR VODP VODR 3.85 2.25 2.85 135 12 4.35 4.30 4.25 4.0 2.4 3.0 150 25 Overcharge Protection Voltage AIC1802B AIC1802C V Overcharge Release Voltage Overdischarge Protection Voltage Overdischarge Release Voltage Overcurrent Protection Voltage Overcharge Delay Time (1) VCC=7V VCC=8.6V, VC=4.3V, CTC=0µF VCC=8.6V, VC=4.3V, CTC=0.47µF VCC=4.8V, VC=2.4V, CTD=0µF VCC=4.8V, VC=2.4V, CTD=0.47µF VCC=7V, VC=3.5V, VCS=0.15V VCC=7V, VC=3.5V, VCS=0.36V VCC=8.6V, VC=4.3V, OC Pin Short to GND V V V mV mS VOIP TOC1 Overcharge Delay Time (2) TOC2 0.7 1.1 1.5 S Overdischarge Delay Time (1) TOD1 12 25 38 mS Overdischarge Delay Time (2) TOD2 0.7 1.1 1.5 S Overcurrent Delay Time (1) TOI1 4 9 14 mS Overcurrent Delay Time (2) TOI2 1.0 2.0 3.0 mS µA V OC Pin Source Current OD Pin Output “H” Voltage 02/26/2008 Rev.1.00 ICO VDL 270 400 530 VCC-0.1 VCC-0.02 www.SiliconStandard.com 3 SS6802 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER OD Pin Output “L” Voltage Charge Detection Threshold Voltage Unbalance Discharge Current VCC=4.8V VCC=8.3V, VC=4V TEST CONDITIONS SYMBOL VDH VCH IUD MIN. TYP. 0.01 MAX. 0.1 UNIT V V -0.55 5.4 -0.4 7.7 10 mA Note1: Specifications are production tested at TA = 25°C. Specifications over the -40°C to 85°C operating Temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). TYPICAL PERFORMANCE CHARACTERISTICS 10.7 10.5 Power-Down Current (µA) VC=1/2VCC TA=25°C 0.8 Supply Current (µA) 0.65 10.3 VC=1/2VCC TA=25°C 0.5 10.1 9.9 0.35 9.7 5.5 6.5 7.5 8.5 0.2 3.8 4.3 4.8 5.3 5.8 Supply Voltage (V) Fig. 1 Supply Current vs. Supply Voltage Fig. 2 Supply Voltage (V) Power-down Current vs. Supply Voltage Overcurrent Protection Voltage (mV) 4.32 150 Overcharge Protection Voltage (V) VCC=7V VC=3.5V 147.5 4.315 AIC1802B 4.31 145 4.305 142.5 4.3 -20 140 -20 -10 0 10 20 30 40 50 60 70 -10 0 10 Temperature (°C) 20 30 40 50 60 70 Temperature (°C) Fig. 4 Overcurrent Protection Voltage vs. Temperature Fig. 3 Overcharge Protection Voltage vs. Temperature 02/26/2008 Rev.1.00 www.SiliconStandard.com 4 SS6802 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 12.5 Power-Down Current (µA) Supply Current (µA) VCC=7V VC=3.5V 11.5 1.1 VCC=4.8V VC=2.4V 0.9 10.5 0.7 9.5 8.5 -20 -10 0 10 0.5 Temperature (°C) 20 30 40 50 60 70 -20 -10 0 10 20 30 40 50 60 70 Temperature (°C) Fig. 6 Power-Down Current vs. Temperature Fig. 5 Supply Current vs. Temperature Overdischarge Protection Voltage 2.420 4.025 2.415 Overcharge Release Voltage (V) 4.020 2.410 4.015 2.405 2.400 4.010 2.395 -20 -10 0 10 Temperature (°C) 20 30 40 50 60 70 4.005 -20 -10 0 10 20 30 40 50 60 70 Temperature (°C) Fig. 8 Overcharge Release Voltage vs. Temperature Fig. 7 Overdischarge Protection Voltage vs. Temperature Overdischarge Release Voltage (V) 3.025 3.020 3.015 3.010 3.005 -20 -10 0 10 20 30 40 50 60 70 70 Temperature (°C) Fig. 9 Overdischarge Release Voltage vs. Temperature 02/26/2008 Rev.1.00 www.SiliconStandard.com 5 SS6802 BLOCK DIAGRAM VCC 8 450 OVERCHARGE DETECTOR 1 OVERCHARGE DELAY CIRCUIT 5 TC OVERDISCHARGE DETECTOR 1 OVERDISCHARGE DELAY CIRCUIT VC 6 UNBALANCE DISCHARGE LOGIC CONTROL 3 POW ERDOW N TD VCC OVERCHARGE DETECTOR 2 450 GND 4 OVERDISCHARGE DETECTOR 2 WAKEUP TIMING GENERATION 1 OC OVERCURRENT DELAY CIRCUIT OVERCURRENT DETECTOR CHARGE DETECTION OD 2 7 CS PIN DESCRIPTIONS PIN 1: OC - PMOS open drain output for control of the charge control MOSFET M2. When overcharge occurs, this pin sources current to switch the external NPN Q1 on, and charging is inhibited by turning off the charge control MOSFET M2. - Output pin for control of discharge control MOSFET When overdischarge occurs, pin goes low to turn off discharge control MOSFET and discharging is inhibited. the M1. this the M1 PIN 5: TC PIN 6: VC - Overcharge delay time setting pin. - To be connected to the positive terminal of the lower cell and the negative terminal of the upper cell. - Input pin for current sensing. Using the drain-source voltage of the discharge control MOSFET M1 (voltage between CS and GND), it senses discharge current during normal mode and detects whether charging current is present during power down mode. PIN 7: CS PIN 2: OD PIN 3: TD - Overdischarge delay time setting pin. PIN 4: GND - Ground pin. This pin is to be connected to the negative terminal of the lower battery cell. 02/26/2008 Rev.1.00 PIN 8: VCC - Power supply pin. It is to be connected to the positive terminal of the upper cell. www.SiliconStandard.com 6 SS6802 APPLICATION INFORMATION THE OPERATION Overcharge Protection When the voltage of either of the battery cells exceeds VOCP (overcharge protection voltage) beyond the overcharge delay time period, charging is inhibited by the turning-off of the charge control MOSFET M2. The overcharge delay time (TOC) defaults to 25mS and can be extended by adding a capacitor CT C . Inhibition of charging is immediately released when the voltage of the overcharged cell becomes lower than VOCR (overcharge release voltage) through discharge. circuit for the cell under overcharge condition. Charge Detection after Overdischarge When overcharge occurs, the discharge control MOSFET M1 turns off and discharging is inhibited. However, charging is still permitted through the parasitic diode of M1. Once the charger is connected to the battery pack, the SS6802 immediately turns on all the timing generation and detection circuitry and goes into normal mode. Charging is determined to be in progress if the voltage between CS and GND is below –0.4V (charge detection threshold voltage VCH) Overdischarge Protection When the voltage of either of the battery cells goes below VODP (overdischarge protection voltage) beyond the overdischarge delay time period, discharging is inhibited by the turning-off of the discharge control MOSFET M1. The overdischarge delay time (TOD) defaults to 25mS and can be extended by adding a capacitor CTD. Inhibition of discharging is immediately released when the voltage of the overdischarged cell becomes higher than VODR (overdischarge release voltage) through charging. Overcurrent Protection In normal mode, the SS6802 continuously monitors the discharge current by sensing the voltage of CS pin. If the voltage of CS pin exceeds VOIP (overcurrent protection voltage) beyond overcurrent delay time TOI period, the overcurrent protection circuit operates and discharging is inhibited by turning-off of the discharge control MOSFET M1. Discharging must be inhibited for at least 256mS after overcurrent takes place to avoid damage to external control MOSFETs due to rapidly switching transient between VBAT+ and VBATterminals. The overcurrent condition returns to the normal mode when the load is released and the impedance between the VBAT+ and VBATterminals is 10MΩ or higher. For the sake of protection of the external MOSFETs, the larger the CS pin voltage (which means the larger discharge current) the shorter the overcurrent delay time. The relationship between voltage of 7 Power-Down after Overdischarge When overdischarge occurs, the SS6802 will go into power-down mode, turning off all the timing generation and detection circuitry to reduce the quiescent current to 0.8µA (VCC=4.8V). In the unusual case where one battery cell is overdischarged while the other under overcharge condition, the SS6802 will turn off all the detection circuits except the overcharge detection 02/26/2008 Rev.1.00 www.SiliconStandard.com SS6802 CS pin and overcurrent delay time TOI is tabulated as below. VCS (V) 150m 200m 300m 360m 1V 3V 5V TOI (S) 9.0m 5.6m 2.8m 2.0m 540µ 290µ 270µ CTC (F) 0µ 0.1µ 0.3µ 0.47µ 0.57µ TOC (S) 25m 320m 890m 1.12 1.43 CTD (F) 0µ 0.1µ 0.3µ TOD (S) 25m 320m 820m 1.08 1.39 Unbalanced Discharge after Overcharge When either of the battery cells is overcharged, the SS6802 will automatically discharge the overcharged cell at about 7.7mA until the voltage of the overcharged cell is equal to the voltage of the other cell. If the voltage of the other cell is below VOCR, the internal cell-balance “bleeding” will proceed until the voltage of the overcharged cell decreases to VOCR. 0.47µ 0.57µ Selection of External Control MOSFETs Because the overcurrent protection voltage is preset, the threshold current for overcurrent detection is determined by the turn-on resistance of the discharge control MOSFET M1. The turn-on resistance of the external control MOSFETs can be determined by the equation: DESIGN GUIDE Adjustment of Overcharge and Overdischarge Delay Time Both the overcharge and overdischarge delay times default to 25mS and can be extended by adding the external capacitors CTC and CTD, respectively. Increasing the capacitance value will increase the delay time. The relationship between capacitance of the external capacitors and delay time is tabulated as below: RON=VOIP/IT (IT is the overcurrent threshold current). turn-on For example, of if the the overcurrent control threshold current IT is designed to be 5A, the resistance external MOSFETs must be 30mΩ. Users should be aware that turn-on resistance of the MOSFET changes with temperature variation due to heat dissipation. It changes with the voltage between gate and source as well. (Turn-on resistance of a MOSFET increases as the voltage between gate and source decreases). Once the turn-on resistance of the external MOSFET changes, the 02/26/2008 Rev.1.00 www.SiliconStandard.com 8 SS6802 overcurrent accordingly. threshold current will change release voltage and bleeding function. The relationship among Vrelease1,Vrelease2, R1, and R2 is shown as following equations: Vrelease1=VOCR+IUD*R1 Vrelease2=VOCR+IUD*R2 where Vrelease1 is Battery 1, real overcharge release voltage Vrelease2 is Battery 2, real overcharge release voltage Therefore, resistance of R1 and R2 should not higher than 30Ω. Otherwise, overcharge release voltage would be higher than overcharge protection voltage and the charging current may oscillate. In addition, if overcharge protection function occurs, SS6802 will discharge the overcharged cell and will stop bleeding function even if the voltage is not equal to the other. The recommended resistance of R1 and R2 is from 20 to 30Ω. Suppressing the Ripple and Disturbance from Charger To suppress the ripple and disturbance from charger, connecting C1 to cell 1 and C2 to cell 2 is necessary. Controlling the Charge Control MOSFET R3, R4, R5 and NPN transistor Q1 are used to switch the charge control MOSFET M2. If overcharge does not occur, no current flows out from OC pin and Q1 are turned off, then M2 is turned on. When overcharge occurs, current flows out from OC pin and Q1 is turned on, which turns off M2 in turn. High resistance for R3, R4, and R5 is recommended for reducing loading of the batteries. Latch-Up Protection at CS Pin R6 is used for latch-up protection when charger is connected under overdischarge condition, and also for overstress protection when charger is connected in reverse. The charge detection function after overdischarge is possibly disabled by larger value of R6. Resistance of 1KΩ is recommended. Effect of C3 C3 has to be applied to the circuit. Because C3 will keep SS6802 to be charged after overdischarge occurred. In addition, when the differential voltage between charger and battery pack is higher than 2.1V and overcharge protection function work, C3 will avoid battery pack from being charged even if the battery voltage lower than 4V (To avoid battery pack from being charged under charger malfunction situation). The battery pack can be charged again till remove it from charger. Selection of R1 and R 2 R1 and R2 are used to avoid large current flow through the battery pack under the situation of IC damage or pin short. On the other hand, resistance of R1 and R2 will affect overcharge 02/26/2008 Rev.1.00 www.SiliconStandard.com 9 SS6802 PHYSICAL DIMENSIONS SOP-8 (unit: mm) D S Y M B O L SOP-8 MILLIMETERS MIN. 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BSC 5.80 0.25 0.40 0° 6.20 0.50 1.27 8° MAX. 1.75 0.25 0.51 0.25 5.00 4.00 H E A A1 B C h X 45° D SEE VIEW B A A e E e H A h L B A1 θ C WITH PLATING BASE METAL 0.25 GAUGE PLANE SEATING PLANE L VIEW B θ Note: 1.Refer to JEDEC MS-012AA. 2.Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3.Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash or protrusion shall not exceed 10 mil per side. 4.Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 02/26/2008 Rev.1.00 www.SiliconStandard.com 10