SS8014GTR

SS8014G 150mA Low-Noise LDO Regulator FEATURES Low output noise of 170µV (rms) Ultra-low no-load supply current of 52µA Low dropout of 100mV at 50mA load Guaranteed 150mA output current Over-temperature and short-circuit protection Output voltage adjustable from 2.5V to 5.5V Max. supply current in shutdown mode < 1µA DESCRIPTION The SS8014G is a low supply-current, low-dropout linear regulator that comes in a space-saving SOT23-5 package. The supply current at no-load is 52µA. In the shutdown mode, the maximum supply current is less than 1µA. Operating voltage range of the SS8014G is from 2.5V to 5.5V. The over-current protection limit is set at 370mA typical and 150mA minimum. An over-temperature protection circuit is built-in to the SS8014G to prevent thermal overload. These power saving features make the SS8014G ideal for use in such battery-powered applications as notebook computers, cellular phones, and PDA’s. APPLICATIONS Notebook Computers Cellular Phones PDAs and other hand-helds Digital Still Cameras and Video Recorders Bar-code Scanners ORDERING INFORMATION SS8014GTR SS8014 in Pb-free SOT-23-5 shipped on tape and reel This device is only available with Pb-free lead finish (second-level interconnect). PIN CONFIGURATION TYPICAL CIRCUIT IN IN OUT R1 OUTPUT VOLTAGE IN 1 5 OUT + - SS8014G ADJ BATTERY CI N 1 µF SHDN GND R2 470 p F C OUT 1 µF GND 2 SS8014G 4 SOT23-5 ADJ SHDN 3 Adjustable mode VOUT =1.250 X ( R2/R 1+1) 1/12/2005 Rev.2.11 www.SiliconStandard.com 1 of 6 SS8014G ABSOLUTE MAXIMUM RATINGS VIN to GND.............................................................. -0.3V to +7V Output Short -Circuit Duration………………….….Infinite SET to GND.……………………………..…..-0.3V to +7V SHDN to GND…………………..………….-0.3V to +7V SHDN to IN….…………………..…………..-7V to +0.3V OUT to GND…………………………-0.3V to (V IN + 0.3V) Continuous Power Dissipation (TA = +25°C) SOT23-5…………….………………………...…..568 mW Operating Temperature Range………....-40°C to +85°C Junction Temperature……………………….……+150°C θ JA….…..……………….…….……….…..…..220°C/Watt Storage Temperature Range…………..-65°C to +160°C Lead Temperature (soldering, 10sec)..………….+300°C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the spec ifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V IN = VOUT +1V ; VSHDN = VIN; CIN = COUT = 1µF = TA = TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Voltage (Note 2) Output V oltage Accuracy Adjustable Output Voltage Range (Note 3) Maximum Output Current Current Limit Quiescent Current Dropout Voltage (Note 3) Line Regulation Load Regulation Output Voltage Temperature Coefficient Output Voltage Noise (10HZ to 100KHZ) SHUTDOWN SHDN Input Threshold SHDN Input Bias Current V IN V OUT V OUT ILIM IQ V DROP ∆V LNR ∆V LDR Variation from spec ified V OUT , IOUT =1mA V OUT = 0V ILOAD = 0mA IOUT = 1mA IOUT = 50mA IOUT =150mA V IN=V O +0.1V to 5.5V, IOUT = 1mA IOUT = 0mA to 150mA CADJ = 470pF CADJ = 10nF Note2 -3 2.5 150 250 5.5 3 5.5 370 52 2 100 340 0.1 8 40 192 170 80 V % V mA mA µA mV 410 0.4 30 %/V mV ppm/°C µV RMS ∆V O / ∆T IOUT = 40mA, TJ = 25°C to 125°C en IL = 150mA V IH V IL I SHDN IQSHDN IADJ TSHDN ∆TSHDN Regulator enabled Regulator shutdown V SHDN = V IN V OUT = 0V V ADJ = 1.3V TA = +25°C TA = +25°C TA = +25°C 2 0.4 0.007 0.06 5 150 15 0.1 1 30 V µA µA nA °C °C Shutdown Supply Current ADJ INPUT ADJ Input Leakage Current THERMAL PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: Limits are 100% production tested at TA= +25°C. Low duty pulse techniques are used during tests to maintain junction temperatures as close to ambient as possible. Note 2: VIN (min) = VOUT +VDROP. Note 3: The dropout voltage is defined as (V IN-VOUT) when VOUT is 100mV below the value of VOUT for VIN = VOUT +2V. 1/12/2005 Rev.2.11 www.SiliconStandard.com 2 of 6 SS8014G PIN DESCRIPTION PIN 1 2 3 NAME IN GND SHDN FUNCTION Regulator Input. Supply voltage can range from +2.5V to +5.5V. Bypass with 1µF to GND Ground. This pin also functions as a heatsink. Solder to large pads or the circuit board ground plane to maximize thermal dissipation. A ctive-Low Shutdown Input. A logic low reduces the supply current to less than 1µA. Connect to IN for normal operation. Adjust (Input): Adjustable regulator feedback input. It can connect to an external resistor divider for adjustable output voltage. A ceramic capacitor of at least 470pF must be connected from ADJ pin to GND to reduce output noise. Regulator Output. Fixed or adjustable from +2.5V to +5.5V. Sources up to 150mA. Bypass with a capacitor of 1µF, < 0.2Ω typical ESR to GND. 4 ADJ 5 OUT APPLICATIONS INFORMATION The block diagram of the SS8014 is shown in Figure 1. It consists of an error amplifier,1.25V bandgap reference, PMOS output transistor, shutdown logic, over-current protection circuit, and over-temperature protection circuit. The SS8014 can be adjusted to a specific output voltage by using two external resistors (Figure 2). The resistors set the output voltage based on the following equation: R2 VOUT =1.250V X +1 R1 Note that the bandgap voltage is relative to the output, as seen in the block diagram. Because traditional regulators normally have the reference voltage relative to ground, they have a different VOUT equation. Resistor values are not critical because ADJ (adjust) has a high input impedance, but for best results use resistors of 470k Ω or less. A capacitor from ADJ to ground provides greatly improved noise performance. IN SHDN SHUTDOWN LOGIC ERROR AMP. + OVER TEMP. & OVER CURRENT PROTECTION 1.25V ref OUT ADJ GND Figure 1. Functional Diagram 1/12/2005 Rev.2.11 www.SiliconStandard.com 3 of 6 SS8014G IN IN + BATTERY CIN 1µF OUT R1 SS8014 ADJ SHDN GND R2 470pF RL OUTPUT VOLTAGE of the chosen package to the ambient air. In the case of a SOT23-5 package, the thermal resistance is typically 220oC/Watt. The die attachment area of the SS8014’s lead frame is connected to pin 2, which is the GND pin. Therefore, the GND pin of SS8014 can carry away the heat of the SS8014 die very effectively. To improve the power diss ipation, connect the GND pin to ground using a large ground plane near the GND pin. Capacitor Selection and Regulator Stability Normally, use a 1µF capacitor on the input and a 1µF capacitor on the output of the SS8014. Larger input capacitor values and lower ESR provide better supply-noise rejection and transient response. A highervalue input capacitor (10µF) may be necessary if large, fast transients are anticipated and the device is located several inches from the power source. P ower-Supply Rejection and Operation from Sources Other than Batteries The SS8014 is designed to deliver low dropout voltages and low quiescent currents in battery powered systems. Power-supply rejection is 42dB at low frequencies. When operating from sources other than batteries, improve supply-noise rejection and transient response by increasing the values of the input and output capacitors, and using passive filtering techniques. Load Transient Considerations The SS8014 load-transient response graphs show two components of the output response: a DC shift of the output voltage due to the different load currents, and the transient response. Typical overshoot for step changes in the load current from 0mA to 100mA is 12mV. Increasing the output capacitor's value and d ecreasing its ESR attenuates transient spikes. Input-Output (Dropout) Voltage A regulator's minimum input -output voltage differential (or dropout voltage) determines the lowest usable supply voltage. In battery -powered systems, this will d etermine the useful end-of-life battery voltage. Because the SS8014 use a P-channel MOSFET pass transistor, the dropout voltage is a function of R DS(ON) multiplied by the load current. COUT 1µF Figure 2. Adjustable Output Using External Feedback Resistors Over Current Protection The SS8014 use a current mirror to monitor the output current. A small portion of the PMOS output transistor’s current is mirrored onto a resistor such that the voltage across this resistor is proportional to the output current. This voltage is compared against the reference voltage. Once the output current exceeds the limit, the PMOS output transistor enters constant current mode. The current is set to 370mA typically. Over Temperature Protection To prevent excessive temperatures from occurring, the SS8014 has a built-in temperature monitoring circuit. When it detects the temperature is above 150oC, the output transistor is turned off. When the temperature drops to below 135oC, the output is turned on again. In this way, the SS8014 is protected against excessive junction temperatures during operation. Shutdown Mode When the SHDN pin is connected to a logic-low voltage, the SS8014 enters shutdown mode. All the analog circuits are turned off completely, which reduces the current consumption to only the leakage current. The output is disconnected from the input. When the output has no load at all, the output voltage will be dis charged to ground through the internal resistor voltage divider. Operating Region and Power Dissipation Since the SS8014 is a linear regulator, its power dissipation is always given by P = IOUT (V IN – VOUT). The max imum power dissipation is given by: PD(MAX) = (TJ–TA)/ Θ JA,=150oC-25oC/220oC/W= 568mW Where (TJ–TA) is the temperature difference the SS8014 die and the ambient air, Θ JA, is the thermal resistance 1/12/2005 Rev.2.11 www.SiliconStandard.com 4 of 6 SS8014G Layout Guide An input capacitance of ~1µF is required between the SS8014 input pin and ground (the amount of the capac itanc e may be increased without limit), This capacitor must be located a distance of not more than 1cm from the input and return to a clean analog ground. This input capacitor filters out the input voltage spike caused by the surge current due to the inductive effect of the package pin and the printed circuit board’s routing wire. Otherwise, the actual voltage at the IN pin may exceed the absolute maximum rating. The output capacitor also must be located a distance of not more than 1cm from output to a clean analog ground. This capacitor filters out the output spike caused by the surge current due to the inductive effect of the package pin and the printed circuit board’s routing wire. Figure 3 is the suggested PCB layout of SS8014. Figure 3. Suggested PCB Layout *Distance between pin & capacitor must be no more than 1cm 1/12/2005 Rev.2.11 www.SiliconStandard.com 5 of 6 SS8014G PHYSICAL DIMENSIONS D C L E H e1 e θ1 Taping Specification A A2 A1 b Note: 1. Package body sizes exclude mold flash protrusions or gate burrs 2. Tolerance ±0.1000 mm (4mil) unless otherwise specified 3. Coplanarity: 0.1000mm 4. Dimension L is measured in gage plane SYMBOLS A A1 A2 b C D E e e1 H L ?1 Feed Direction SOT23-5 Package Orientation MIN 1.00 0.00 0.70 0.35 0.10 2.70 1.40 --------2.60 0.37 1º DIMENSIONS IN MILLIMETERS NOM 1.10 ----0.80 0.40 0.15 2.90 1.60 1.90(TYP) 0.95 2.80 -----5º MAX 1.30 0.10 0.90 0.50 0.25 3.10 1.80 --------3.00 ----9º Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 1/12/2005 Rev.2.11 www.SiliconStandard.com 6 of 6