SS809N-46GU

SS809/810G 3-Pin Microprocessor Reset Circuits FEATURES Ultra-low supply current 1µA (typ.) Guaranteed reset valid to Vcc=0.9V Available in three output types: Open-drain active low (SS809N-xxGx) Push-pull active low (SS809-xxGx) Push-pull active high (SS810-xxGx) Power-on reset pulse width min. 140ms Internally fixed threshold 2.3V, 2.6V, 2.9V, 3.1V, 4.0V, 4.4V, 4.6V Tight voltage threshold tolerance: 1.5% Packaged in RoHS-compliant SOT-23-3 These devices provide valid signals in applications with Vcc ranging from 6.0V down to 0.9V. The reset signal lasts for a minimum period of 140ms whenever the VCC supply voltage falls below a preset threshold. Both the SS809G and SS810G were designed with a reset comparator to help identify invalid signals lasting less than 140ms. The only difference between the two devices is that one has an active -low RESET output and the other an active -high RESET output . Low supply current (1µA) makes the SS809G and SS810G ideal for portable equipment. The devices are available in a SOT-23-3 package. DESCRIPTION The SS809G and SS810G are low-power microprocessor (µP) supervisory circuits used to monitor power supplies in µP and digital systems. They improve circuit reliability and reduce cost by eliminating external components. APPLICATIONS l l l l Notebook Computers Digital Still Cameras PDAs Critical Microprocessor Monitoring TYPICAL APPLICATION CIRCUIT VCC VCC SS809G ( SS810G) RESET (RESET) GND VCC µP RESET INPUT GND Push -Pull Output 9/20/2006 Rev.3.01 www.SiliconStandard.com 1 of 8 SS809/810G ORDERING INFORMATION SS809X-XXGU XX SS810 -XXGU XX Packing type TR: T ape and reel SOT-23-3 TOP VIEW 1: GND 2: RESET (RESET) 3: VCC 3 PIN CONFIGURATION 1 2 Package type GU: RoHS-compliant Pb-free SOT-23-3 Reset threshold voltage 23: 2.3V 26: 2.6V 29: 2.9V 31: 3.1V 40: 4.0V 44: 4.4V 46: 4.6V Output type Default: Push-Pull type N: N-ch open-drain type Example: SS809 -31GU TR à 3.1V , push- pull version in RoHS-compliant SOT -23-3 , shipped in tape and reel SOT -23 Part Marking Part No. SS809-23GU SS809-26GU SS809-29GU SS809-31GU SS809-40GU SS809-44GU SS809-46GU Marking RA23P RA26P RA29P RA31P RA40P RA44P RA46P Part No. SS809N-23GU SS809N-26GU SS809N-29GU SS809N-31GU SS809N-40GU SS809N-44GU SS809N-46GU Marking RB23P RB26P RB29P RB31P RB40P RB44P RB46P Part No. SS810-23GU SS810-26GU SS810-29GU SS810-31GU SS810-40GU SS810-44GU SS810-46GU Marking RD23P RD26P RD29P RD31P RD40P RD44P RD46P 9/20/2006 Rev.3.01 www.SiliconStandard.com 2 of 8 SS809/810G ABSOLUTE MAXIMUM RATINGS VCC RESET, RESET Input Current (V CC) Output Current (RESET or RESET ) Continuous Power Dissipation (TA = +70°C) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 sec -0.3V ~6.5V -0.3V ~ (VCC+0.3V) 20mA 20mA 320mW -40°C ~ 85°C - 65°C ~ 125°C 260°C Note1: Any stress beyond the Absolute Maximum Ratings above may cause permanent damage to the device. T EST CIRCUIT 3 2 Vin VCC GND RESET Iin SS809G 1 9/20/2006 Rev.3.01 www.SiliconStandard.com 3 of 8 SS809/810G ELECTRICAL CHARACTERISTICS (Typical values are at TA=25° C, unless otherwise specified.) PARAMETER Operating Voltage Range Supply Current TEST CONDITIONS VCC = VTH +0.1V SS809-23 SS809-26 SS809-29 Reset Threshold VTH SS809-31 SS809-40 SS809-44 SS809-46 VCC to Reset Delay Reset Active Timeout Period TRD TRP VOH VOL VOH VOL TA=+25°C TA= -40°C to +85°C TA=+25°C TA= -40°C to +85°C TA=+25°C TA= -40°C to +85°C TA=+25°C TA= -40°C to +85°C TA=+25°C TA= -40°C to +85°C TA=+25°C TA= -40°C to +85°C TA=+25°C TA=-40°C to +85°C TA=+25°C TA= -40°C to +85°C 2.265 2.254 2.561 2.548 2.857 2.842 3.054 3.038 3.940 3.920 4.334 4.312 4.531 4.508 20 140 100 0.8V CC 0.2Vcc 0.8V CC 0.2Vcc 230 560 1030 4.6 4.4 4.0 3.1 2.9 2.6 MIN. 0.9 1 2.3 TYP. MAX. 6 3 2.335 2.346 2.639 2.652 2.944 2.958 3.147 3.162 4.060 4.080 4.466 4.488 4.669 4.692 µS mS V V UNIT V µA SYMBOL VCC ICC VCC=VTH to (VTH -0.1V), VTH=3.1V VCC = VTH ( MAX) RESET Output Voltage VCC=VTH+0.1V, ISOURCE =1mA VCC=VTH - 0.1V, ISINK =1mA VCC=VTH-0.1V, ISOURCE =1mA VCC=VTH+0.1V, ISINK =1mA RESET Output Voltage V Note2: RESET output is for the SS809G; RESET output is for the SS810G. Note3: Specifications for operating temperature ranges from -40°C to 85°C are guaranteed by Statistical Quality Controls (SQC), with no production testing. 9/20/2006 Rev.3.01 www.SiliconStandard.com 4 of 8 SS809/810G TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.4 120 Power -Down Reset Delay (µ s ) 110 100 90 80 70 60 50 40 30 20 10 0 - 60 - 40 - 20 0 20 40 VTH=2.3V S upply Current (µ A) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 - 40 - 20 0 20 VTH=2.3V VO D=VTH-VCC VTH=3.1V VTH=4.6V VOD=50mV VOD=100mV VOD=200mV 40 60 80 100 60 80 100 Temperature (° C) Fig 1 Supply Current vs. Temperature 240 Temperature (° C) Fig 2 Power-Down Reset Delay vs. Temperature Power -Down Reset Delay (µ s ) Power -Down Reset Delay (µ s ) 220 200 180 160 140 120 100 80 60 40 20 0 -60 - 40 - 20 VTH=3.1V VO D=VTH-VCC 400 VOD=50mV VTH=4.6V VOD=VTH-VCC 300 VOD=50mV 200 VOD=100mV 100 VOD=100mV VOD=200mV 0 20 40 60 80 100 VOD=200mV 0 -60 - 40 - 20 0 20 40 60 80 100 Temperature (° C) Fig 3 Power-Down Reset Delay vs. Temperature 6 00 Temperature (° C) Fig 4 Power-Down Reset Delay vs. Temperature Normalized Reset Threshold (V) 1.010 1.005 1.000 0.995 0.990 0.985 -40 -20 0 VTH=4.6V Power -Up Reset Timeout (ms) 1.015 5 00 4 00 VTH=3.1V 3 00 2 00 VTH=3.1V VTH=4.6V VTH=2.3V VTH=2.3V 1 00 0 -60 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 5 Normalized Reset Threshold vs. Temperature Temperature (° C) Fig 6 Power-Up Reset Timeout vs. Temperature 9/20/2006 Rev.3.01 www.SiliconStandard.com 5 of 8 SS809/810G BLOCK DIAGRAM VCC R1 Bandgap + RESET Reset Generator NMOS R2 GND N-ch Open-Drain Type VCC R1 Bandgap + Reset Generator RESET (RESET) R2 GND Push-Pull Type PIN DESCRIPTIONS GND Pin : Ground. Active low output pin. RESET Output remains low while Vcc is below the reset Active high output pin. RESET output remains high while Vcc is below the reset threshold. Supply voltage. RESET Pin (SS809G) : RESET P in (SS810G) Vcc Pin : : 9/20/2006 Rev.3.01 www.SiliconStandard.com 6 of 8 SS809/810G DETAIL ED DESCRIPTIONS OF TECHNICAL TERMS threshold, and RESET remains low for the reset RESET OUTPUT The µP will be activated at a valid reset state. These µP supervisory circuits assert reset to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is guaranteed to be a logic low for VTH>VCC>0.9V. Once VCC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Any time VCC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer is activated after VCC returns above the reset timeout period. BENEFITS OF HIGHLY ACCURATE RESET THRESHOLD The SS809G and SS810G with specified voltage as 5V± 10% or 3V±10% are ideal for systems using a 5V±5% or 3V ± 5% power supply. The reset is guaranteed to assert after the power supply falls out of regulation, but before the power drops below the minimum specified operating voltage range of the system ICs. The pre-trimmed thresholds reduc e the range over which an undesirable reset may occur. APPLICATION INFORMATION NEGATIVE-GOING VCC TRANSIENTS I n addition to issuing a reset to the µ P d uring power-up, power-down, and brownout conditions, the SS809G series are relatively resistant to short -duration negative-going VCC transients. INTERFACING TO A MICROPROCESSOR WITH ENSURING A VALID RESET OUTPUT DOWN TO VCC=0 When VCC falls below 0.9V, the SS809G RESET output no longer sinks current; it becomes an open circuit. In this case, high-impedance CMOS logic inputs connected to BIDIRECTIONAL RESET PINS The RESET output on the SS809N is open drain, and this device interfaces easily with µPs that have bidirectional supervisor’s reset pins. Connecting directly the to µP the o f 0 .9V. However in applications where R ESET must be valid down to 0V, adding a pull-down resistor to RESET causes any leakage currents to flow to ground, holding RESET low. RESET output RESET can drift to microcontroller’s RESET pin with a single pull-up resistor allows either device to assert reset. undetermined voltages. Therefore, the SS809G/810G are perfect for most CMOS applications down to VCC 9/20/2006 Rev.3.01 www.SiliconStandard.com 7 of 8 SS809/810G PHYSICAL DIMENSIONS SOT -23-3 (unit: mm) D C L E H θ1 SYMBOL A A1 A2 b C D E MIN 1.00 — 0.70 0.35 0.10 2.70 1.40 MAX 1.30 0.10 0.90 0.50 0.25 3.10 1.80 e A2 A A1 b e H L θ1 1.90 (TYP) 2.60 0.37 1° 3.00 — 9° In formation furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/20/2006 Rev.3.01 www.SiliconStandard.com 8 of 8