SSM25G45EM

SSM25G45EM N-CHANNEL INSULATED-GATE BIPOLAR TRANSISTOR High input impedance High peak current capability C C C C VCE ICP 450V 150A C 4.5V gate drive G SO-8 E E E G E Absolute Maximum Ratings Symbol VCE VGE VGEP ICP PD @ TC=25°C TSTG TJ 1 Parameter Collector-Emitter Voltage Gate-Emitter Voltage Pulsed Gate-Emitter Voltage Pulsed Collector Current Maximum Power Dissipation Storage Temperature Range Operating Junction Temperature Range Rating 450 ±6 ±8 150 2.5 -55 to 150 -55 to 150 Units V V V A W °C °C Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol IGES ICES VCE(sat) VGE(th) Qg Qge Qgc td(on) tr td(off) tf Cies Coes Cres RthJA 1 Parameter Gate-Emitter Leakage Current Collector-Emitter Leakage Current (Tj=25°C) Test Conditions VGE=± 6V, VCE=0V VCE=450V, VGE=0V VGE=4.5V, ICP=150A (Pulsed) Min. 0.35 - Typ. 6 64.5 7 30 11.5 24.5 150 3.3 2227 200 79 - Max. 10 10 8 1.2 50 Units µA µA V V nC nC nC ns ns ns µs pF pF pF °C/W Collector-Emitter Saturation Voltage Gate Threshold Voltage Total Gate Charge Gate-Emitter Charge Gate-Collector Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance VCE=VGE, IC=250uA IC=50A VCE=360V VGE=5V VCC=225V IC=50A RG=25Ω VGE=5V VGE=0V VCE=25V f=1.0MHz Thermal Resistance Junction-Ambient Notes: 1.Surface mounted on 1 in2 copper pad of FR4 board ; 125°C/W when mounted on min. copper pad. 9/21/2004 Rev.2.01 www.SiliconStandard.com 1 of 4 SSM25G45EM 180 140 160 T A =25 o C 140 5.0V 4.5V 4.0V IC , Collector Current (A) 120 T A =150 o C 5.0V 4.5V 4.0V ID , Drain Current (A) 100 120 100 3.0V 80 3.0V 80 60 60 2.0V 40 40 2.0V 20 20 VG=1.0V 0 0 2 4 6 8 10 0 2 4 6 8 VG=1.0V 10 12 0 V CE , Collector-Emitter Voltage (V) V CE , Collector-Emitter Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 160 10 V CE =4.5V IC , Collector Current(A) 120 V GE =4.5V VCE(sat),Saturation Voltage(V) 8 I C =130A 25°C 70°C 125°C T A =150°C 6 80 I C =100A 4 40 I C =50A 2 0 0 1 2 3 4 5 6 0 0 20 40 60 80 100 120 140 160 V GE , Cate-Emitter Voltage (V) Junction Temperature ( o C) Fig 3. Collector Current vs. Gate-Emitter Voltage 1.5 Fig 4. Collector- Emitter Saturation Voltage vs. Junction Temperature 200 ICP, Peak Collector Current (A) -50 0 50 100 150 1.2 160 VGE(th) (V) 0.9 120 0.6 80 0.3 40 0 0 0 1 2 3 4 5 6 7 Junction Temperature ( o C) V GE , Gate-to-Emitter Voltage (V) Fig 5. Gate Threshold Voltage vs. Junction Temperature 9/21/2004 Rev.2.01 Fig 6. Minimum Gate Drive Area www.SiliconStandard.com 2 of 4 SSM25G45EM 10000 f=1.0MHz 12 11 Cies Capacitance (pF) 1000 VGE , Gate -Emitter Voltage (V) 10 9 8 7 6 5 4 3 2 1 I CP =50A V CC =360V Coes 100 Cres 10 1 5 9 13 17 21 25 29 0 0 30 60 90 120 150 VCE, Collector-Emitter Voltage (V) Q G , Gate Charge (nC) Fig 7. Typical Capacitance Characterisitics Fig 8. Gate Charge Waveform VCE RC TO THE OSCILLOSCOPE 90% CV CE RG G 225 V E + 10% VGE V GE - 5V td(on) tr td(off) tf Fig 9. Switching Time Test Circuit Fig 10. Switching Time Waveform VCE C G TO THE OSCILLOSCOPE Flasher Vtrig CM IGBT + _ VCM 300V V GE RG E + - 1~3mA I G IC VG VCM = 300V CM =100uF ICP = 150A VG =5V Fig 11. Gate Charge Test Circuit Fig 12. Application Test Circuit 9/21/2004 Rev.2.01 www.SiliconStandard.com 3 of 4 SSM25G45EM In formation furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/21/2004 Rev.2.01 www.SiliconStandard.com 4 of 4