SST25VF020B-80-4C-QAE

2 Mbit SPI Serial Flash SST25VF020B SST25VF040B4Mb Serial Peripheral Interface (SPI) flash memory Data Sheet FEATURES: • Single Voltage Read and Write Operations – 2.7-3.6V • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • High Speed Clock Frequency – Up to 80 MHz • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Read Current: 10 mA (typical) – Standby Current: 5 µA (typical) • Flexible Erase Capability – Uniform 4 KByte sectors – Uniform 32 KByte overlay blocks – Uniform 64 KByte overlay blocks • Fast Erase and Byte-Program: – Chip-Erase Time: 35 ms (typical) – Sector-/Block-Erase Time: 18 ms (typical) – Byte-Program Time: 7 µs (typical) • Auto Address Increment (AAI) Programming – Decrease total chip programming time over Byte-Program operations • End-of-Write Detection – Software polling the BUSY bit in Status Register – Busy Status readout on SO pin in AAI Mode • Hold Pin (HOLD#) – Suspends a serial sequence to the memory without deselecting the device • Write Protection (WP#) – Enables/Disables the Lock-Down function of the status register • Software Write Protection – Write protection through Block-Protection bits in status register • Temperature Range – Commercial: 0°C to +70°C – Industrial: -40°C to +85°C • Packages Available – 8-lead SOIC (150 mils) – 8-contact WSON (6mm x 5mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The 25 series Serial Flash family features a four-wire, SPIcompatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF020B devices are enhanced with improved operating frequency and even lower power consumption. SST25VF020B SPI serial flash memories are manufactured with SST proprietary, highperformance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25VF020B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF020B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25VF020B device is offered in 8-lead SOIC (150 mils) and 8-contact WSON (6mm x 5mm) packages. See Figure 2 for pin assignments. © 2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 1 The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Address Buffers and Latches X - Decoder SuperFlash Memory Y - Decoder Control Logic I/O Buffers and Data Latches Serial Interface CE# SCK SI SO WP# HOLD# 1417 B1.0 FIGURE 1: Functional Block Diagram ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 2 2 Mbit SPI Serial Flash SST25VF020B Data Sheet PIN DESCRIPTION CE# SO WP# VSS 1 2 8 7 VDD HOLD# SCK SI CE# SO WP# VSS 1 8 VDD HOLD# SCK SI 2 7 Top View 3 4 6 5 3 Top View 6 4 5 8-Lead SOIC 1417 08-soic S2A P1.0 8-Contact WSON 1417 08-wson QA P2.0 FIGURE 2: Pin Assignments TABLE 1: Pin Description Symbol SCK Pin Name Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin. See “Hardware End-of-Write Detection” on page 12 for details. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To temporarily stop serial communication with SPI flash memory without resetting the device. To provide power supply voltage: 2.7-3.6V for SST25VF020B T1.0 1417 SI SO Serial Data Input Serial Data Output CE# WP# HOLD# VDD VSS Chip Enable Write Protect Hold Power Supply Ground ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 3 2 Mbit SPI Serial Flash SST25VF020B Data Sheet MEMORY ORGANIZATION The SST25VF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte overlay blocks and 64 KByte overlay erasable blocks. The SST25VF020B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. DEVICE OPERATION The SST25VF020B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). CE# MODE 3 MODE 3 MODE 0 SCK SI SO MODE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 1417 SPIprot.0 HIGH IMPEDANCE FIGURE 3: SPI Protocol ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 4 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Hold Operation The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 4 for Hold timing. SCK HOLD# Active Hold Active Hold Active 1417 HoldCond.0 FIGURE 4: Hold Condition Waveform Write Protection SST25VF020B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register, and the Top/ Bottom Sector Protection Status bits (TSP and BSP) in Status Register 1, provide Write protection to the memory array and the status register. See Table 5 for the Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled. TABLE 2: Conditions to execute Write-StatusRegister (WRSR) Instruction WP# L L H BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed T2.0 1417 ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 5 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or TABLE 3: Software Status Register Bit 0 1 2 3 4:5 6 Name BUSY WEL BP0 BP1 RES AAI Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicates current level of block write protection (See Table 5) Indicates current level of block write protection (See Table 5) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP1, BP0 are read-only bits 0 = BP1, BP0 are read/writable Default at Power-up 0 0 1 1 0 0 Read/Write R R R/W R/W N/A R Program operation, the status register may be read only to determine the completion of an operation in progress. Table 3 describes the function of each bit in the software status register. 7 BPL 0 R/W T3.0 1417 Software Status Register 1 The Software Status Register 1 is an additional register that contains Top Sector and Bottom Sector Protection bits. These register bits are read/writable and determine the TABLE 4: Software Status Register 1 Bit 0:1 2 Name RES TSP Function Reserved for future use Top Sector Protection status 1 = Indicates highest sector is write locked 0 = Indicates highest sector is Write accessible Bottom Sector Protection status 1 = Indicates lowest sector is write locked 0 = Indicates lowest sector is Write accessible Reserved for future use Default at Power-up 0 0 Read/Write N/A R/W lock and unlock status of the top and bottom sectors. Table 4 describes the function of each bit in the Software Status Register 1. 3 BSP 0 R/W 4:7 RES 0 N/A T4.0 1417 Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 6 2 Mbit SPI Serial Flash SST25VF020B Data Sheet • • • • Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register instructions Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be software protected against any memory Write (Program or Erase) operation. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP1 and BP0 are set to 1. Block Protection Lock-Down (BPL) WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP1, and BP0 bits of the status register and BSP and TSP of Status Register 1. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. • • • • Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. TABLE 5: Software Status Register Block Protection FOR SST25VF020B1 Status Register Bit2 Protection Level 0 1 (1/4 Memory Array) 1 (1/2 Memory Array) 1 (Full Memory Array) BP1 0 0 1 1 BP0 0 1 0 1 Protected Memory Address 2 Mbit None 030000H-03FFFFH 020000H-03FFFFH 000000H-03FFFFH T5.0 1417 1. X = Don’t Care (RESERVED) default is “0 2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected) Top-Sector Protection/Bottom-Sector Protection The Top-Sector Protection (TSP) and Bottom-Sector Protection (BSP) bits independently indicate whether the highest and lowest sector locations are Write locked or Write accessible. When TSP or BSP is set to ‘1’, the respective sector is Write locked; when set to ‘0’ the respective sector is Write accessible. If TSP or BSP is set to '1' and if the top or bottom sector is within the boundary of the target address range of the program or erase instruction, the initiated instruction (Byte-Program, AAI-Word Program, Sector-Erase, Block-Erase, and Chip-Erase) will not be executed. Upon power-up, the TSP and BSP bits are automatically reset to ‘0’. ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 7 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF020B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of instructions is provided in Table 6. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the rising edge TABLE 6: Device Operation Instructions Instruction Read High-Speed Read 32 KByte Block-Erase4 Description Read Memory Read Memory at higher speed Op Code Cycle1 0000 0011b (03H) 0000 1011b (0BH) 0010 0000b (20H) Address Cycle(s)2 3 3 3 3 3 0 3 3 0 0 0 0 0 0 3 0 0 0 Dummy Cycle(s) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Cycle(s) 1 to ∞ 1 to ∞ 0 0 0 0 1 2 to ∞ 1 to ∞ 1 to ∞ 0 1 or 2 0 0 1 to ∞ 3 to ∞ 0 0 T6.0 1417 of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-StatusRegister instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. 4 KByte Sector-Erase3 Erase 4 KByte of memory array Erase 32 KByte block of memory array 0101 0010b (52H) Erase Full Memory Array To Program One Data Byte Read-Status-Register Read-Status-Register 1 Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID JEDEC ID read Enable SO to output RY/BY# status during AAI programming Disable SO to output RY/BY# status during AAI programming 0110 0000b (60H) or 1100 0111b (C7H) 0000 0010b (02H) 0000 0101b (05H) 0011 0101b (35H) 0101b 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) or 1010 1011b (ABH) 1001 1111b (9FH) 0111 0000b (70H) 1000 0000b (80H) 64 KByte Block-Erase5 Erase 64 KByte block of memory array 1101 1000b (D8H) Chip-Erase Byte-Program AAI-Word-Program6 RDSR7 RDSR1 EWSR WRSR WREN WRDI RDID8 JEDEC-ID EBSY DBSY Auto Address Increment Programming 1010 1101b (ADH) 1. 2. 3. 4. 5. 6. One bus cycle is eight clock periods. Address bits above the most significant bit of each density can be VIL or VIH. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0=1. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 8 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Read (33 MHz) The Read instruction, 03H, supports up to 33 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. Once the data from address location 3FFFFH has been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read sequence. CE# MODE 3 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 SCK MODE 0 SI MSB SO 03 ADD. MSB HIGH IMPEDANCE ADD. ADD. N DOUT MSB 1417 ReadSeq.0 N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT FIGURE 5: Read Sequence ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 9 2 Mbit SPI Serial Flash SST25VF020B Data Sheet High-Speed-Read (80 MHz) The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-SpeedRead cycle. See Figure 6 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wraparound) of the address space. Once the data from address location 3FFFH has been read, the next output will be from address location 00000H. CE# MODE 3 SCK MODE 0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB SO 0B ADD. MSB HIGH IMPEDANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) 1417 HSRdSeq.0 FIGURE 6: High-Speed-Read Sequence ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 10 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The ByteProgram instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence. CE# MODE 3 012345678 15 16 23 24 31 32 39 SCK MODE 0 SI MSB 02 ADD. MSB ADD. ADD. DIN MSB LSB SO HIGH IMPEDANCE 1417 ByteProg.0 FIGURE 7: Byte-Program Sequence ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 11 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Auto Address Increment (AAI) Word-Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes or entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI Word Programming sequence, the only valid instructions are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users have three options to determine the completion of each AAI Word program cycle: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the software status register or wait TBP. Refer to EndOf-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI Word Program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data is input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) will be programmed into the initial address [A23-A1] with A0=0, the second byte of Data (D1) will be programmed into the initial address [A23-A1] with A0=1. CE# must be driven high before the AAI Word Program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. See Figures 10 and 11 for AAI Word programming sequence. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0) and the AAI bit (AAI=0). End-of-Write Detection There are three methods to determine completion of a program cycle during AAI Word programming: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The hardware end-of-write detection method is described in the section below. Hardware End-of-Write Detection The hardware end-of-write detection method eliminates the overhead of polling the Busy bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming. (see Figure 8) The 8-bit command, 70H, must be executed prior to executing an AAI Word-Program instruction. Once an internal programming operation begins, asserting CE# will immediately drive the status of the internal flash status on the SO pin. A “0” indicates the device is busy and a “1” indicates the device is ready for the next instruction. Deasserting CE# will return the SO pin to tri-state. The 8-bit command, 80H, disables the Serial Output (SO) pin to output busy status during AAI-Word-program operation and return SO pin to output Software Status Register data during AAI Word programming. (see Figure 9) CE# MODE 3 01234567 SCK MODE 0 SI MSB 70 HIGH IMPEDANCE 1417 EnableSO.0 SO FIGURE 8: Enable SO as Hardware RY/BY# during AAI Programming ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 12 2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 01234567 SCK MODE 0 SI MSB 80 HIGH IMPEDANCE 1417 DisableSO.0 SO FIGURE 9: Disable SO as Hardware RY/BY# during AAI Programming CE# 0 78 15 16 23 24 31 32 39 40 47 0 78 15 16 23 0 78 15 16 23 0 7 0 78 15 MODE 3 SCK SI MODE 0 AD A A A D0 D1 AD D2 D3 AD Dn-1 Last 2 Data Bytes Dn WRDI WDRI to exit AAI Mode RDSR Load AAI command, Address, 2 bytes data SO Check for Flash Busy Status to load next valid1 command DOUT Wait TBP or poll Software Status register to load any command Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming 1417 AAI.HW.0 FIGURE 10: Auto Address Increment (AAI) Word-Program Sequence with Hardware End-of-Write Detection ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 13 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Wait TBP or poll Software Status register to load next valid1 command CE# 0 78 15 16 23 24 31 32 39 40 47 0 78 15 16 23 0 78 15 16 23 0 7 0 78 15 MODE 3 SCK SI MODE 0 AD A A A D0 D1 AD D2 D3 AD Dn-1 Last 2 Data Bytes Dn WRDI WDRI to exit AAI Mode RDSR Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command DOUT Wait TBP or poll Software Status register to load any command 1417 AAI.SW.0 FIGURE 11: Auto Address Increment (AAI) Word-Program Sequence with Software End-of-Write Detection ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 14 2 Mbit SPI Serial Flash SST25VF020B Data Sheet 4-KByte Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 12 for the Sector-Erase sequence. CE# MODE 3 012345678 15 16 23 24 31 SCK MODE 0 SI MSB 20 ADD. MSB ADD. ADD. SO HIGH IMPEDANCE 1417 SecErase.0 FIGURE 12: Sector-Erase Sequence ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 15 2 Mbit SPI Serial Flash SST25VF020B Data Sheet 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The 32-Kbyte BlockErase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The 64-Kbyte Block-Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A23-A0]. Address bits [AMS-A15] are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase cycles. See Figures 13 and 14 for the 32-KByte BlockErase and 64-KByte Block-Erase sequences. CE# MODE 3 012345678 15 16 23 24 31 SCK MODE 0 SI MSB 52 ADDR MSB ADDR ADDR SO HIGH IMPEDANCE 1417 32KBklEr.0 FIGURE 13: 32-KByte Block-Erase Sequence CE# MODE 3 012345678 15 16 23 24 31 SCK MODE 0 SI MSB D8 ADDR MSB ADDR ADDR SO HIGH IMPEDANCE 1417 63KBlkEr.0 FIGURE 14: 64-KByte Block-Erase Sequence ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 16 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase sequence. CE# MODE 3 01234567 SCK MODE 0 SI MSB 60 or C7 HIGH IMPEDANCE 1417 ChEr.0 SO FIGURE 15: Chip-Erase Sequence Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows reading of the status register. The Status Register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. ReadStatus-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR instruction sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK SI SO MODE 0 05 MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1417 RDSRseq.0 FIGURE 16: Read-Status-Register (RDSR) Sequence Read-Status-Register (RDSR1) The Read-Status-Register 1 (RDSR1) instruction allows reading of the status register 1. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register 1 is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 17 for the RDSR instruction sequence. ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 17 2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK SI SO MODE 0 35 MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1417 RDSR1seq.0 FIGURE 17: Read-Status-Register 1 (RDSR1) Sequence Write-Enable (WREN) The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. CE# MODE 3 01234567 SCK MODE 0 SI MSB 06 HIGH IMPEDANCE 1417 WREN.0 SO FIGURE 18: Write Enable (WREN) Sequence Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any program operation in progress may continue up to TBP after executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed. ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 18 2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 01234567 SCK MODE 0 SI MSB 04 HIGH IMPEDANCE 1417 WRDI.0 SO FIGURE 19: Write Disable (WRDI) Sequence Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write-StatusRegister instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 19 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and WRSR for byte-data input sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the CE# MODE 3 BPL bit is disabled and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL functions. 01234567 MODE 3 MODE 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK MODE 0 SI MSB SO 50 or 06 MSB 01 HIGH IMPEDANCE STATUS REGISTER IN 76543210 MSB 1417 EWSR.0 FIGURE 20: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Byte-Data Input Sequence The Write-Status-Register instruction also writes new values to the Status Register 1. To write values to Status Register 1, the WRSR sequence needs a word-data input—the first byte being the Status Register bits, followed by the second byte Status Register 1 bits. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 21 for EWSR or WREN and WRSR instruction word-data input sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to ‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status registers, but cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1, TSP and BSP bits , in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the low-tohigh transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BPL, BP0, BP1, TSP and , BSP bits at the same time. See Table 2 for a summary description of WP# and BPL functions. ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 20 2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 01234567 MODE 3 MODE 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK MODE 0 SI MSB SO 50 or 06 MSB 01 HIGH IMPEDANCE STATUS STATUS REGISTER REGISTER 1 7654321076543210 MSB MSB 1417 EWSR1.0 FIGURE 21: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Word-Data Input Sequence The WRSR instruction can either execute a byte-data or a word-data input. Extra data/clock input, or within byte-/ word-data input, will not be executed. The reason for the JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF020B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 8CH, identifies the device as SST25VF020B. The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output. byte support is for backward compatibility to products where WRSR instruction sequence is followed by only a byte-data. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK MODE 0 SI HIGH IMPEDANCE 9F SO BF MSB MSB 25 8C 1417 JEDECID.1 FIGURE 22: JEDEC Read-ID Sequence TABLE 7: JEDEC Read-ID Data Device ID Manufacturer’s ID Byte1 BFH Memory Type Byte 2 25H Memory Capacity Byte 3 8CH T7.0 1417 ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 21 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF020B and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#. Refer to Tables 7 and 8 for device identification data. CE# MODE 3 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 SCK MODE 0 SI MSB 90 or AB 00 00 ADD1 MSB SO HIGH IMPEDANCE MSB BF Device ID BF Device ID HIGH IMPEDANCE Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. Device ID = 8CH for SST25VF020B 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1417 RdID.0 FIGURE 23: Read-ID Sequence TABLE 8: Product Identification Address Manufacturer’s ID Device ID SST25VF020B 00001H 8CH T8.0 1417 Data BFH 00000H ©2010 Silicon Storage Technology, Inc. S71417-02-000 04/10 22 2 Mbit SPI Serial Flash SST25VF020B Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (