SST25VF512A

512 Kbit SPI Serial Flash SST25VF512A SST25VF512A512Kb Serial Peripheral Interface (SPI) flash memory Data Sheet FEATURES: • Single 2.7-3.6V Read and Write Operations • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • 33 MHz Max Clock Frequency • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Read Current: 7 mA (typical) – Standby Current: 8 µA (typical) • Flexible Erase Capability – Uniform 4 KByte sectors – Uniform 32 KByte overlay blocks • Fast Erase and Byte-Program: – Chip-Erase Time: 70 ms (typical) – Sector- or Block-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical) • Auto Address Increment (AAI) Programming – Decrease total chip programming time over Byte-Program operations • End-of-Write Detection – Software Status • Hold Pin (HOLD#) – Suspends a serial sequence to the memory without deselecting the device • Write Protection (WP#) – Enables/Disables the Lock-Down function of the status register • Software Write Protection – Write protection through Block-Protection bits in status register • Temperature Range – Commercial: 0°C to +70°C – Industrial: -40°C to +85°C – Extended: -20°C to +85°C • Packages Available – 8-lead SOIC 150 mil body width – 8-contact WSON (5mm x 6mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25VF512A SPI serial flash memory is manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25VF512A device significantly improves performance, while lowering power consumption. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25VF512A device operates with a single 2.7-3.6V power supply. The SST25VF512A device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pin assignments. © 2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 1 The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 512 Kbit SPI Serial Flash SST25VF512A Data Sheet FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X - Decoder SuperFlash Memory Y - Decoder Control Logic I/O Buffers and Data Latches Serial Interface 1264 B1.0 CE# SCK SI SO WP# HOLD# ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 2 512 Kbit SPI Serial Flash SST25VF512A Data Sheet PIN DESCRIPTION CE# SO WP# VSS 1 2 8 7 VDD HOLD# SCK SI CE# SO WP# VSS 1 8 VDD HOLD# SCK SI 2 7 Top View 3 4 6 5 1264 08-soic P1.0 3 Top View 6 4 5 1264 08-wson P2.0 8-LEAD SOIC 8-CONTACT WSON FIGURE 1: PIN ASSIGNMENTS TABLE 1: PIN DESCRIPTION Symbol Pin Name SCK Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To temporarily stop serial communication with SPI flash memory without resetting the device. To provide power supply (2.7-3.6V). T1.0 1264 SI SO CE# WP# HOLD# VDD VSS Serial Data Input Serial Data Output Chip Enable Write Protect Hold Power Supply Ground ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 3 512 Kbit SPI Serial Flash SST25VF512A Data Sheet PRODUCT IDENTIFICATION TABLE 2: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST25VF512A 00001H 48H T2.0 1264 DEVICE OPERATION The SST25VF512A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF512A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. Data BFH 00000H MEMORY ORGANIZATION The SST25VF512A SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay blocks. CE# MODE 3 MODE 3 MODE 0 SCK SI SO MODE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 1264 F02.0 HIGH IMPEDANCE FIGURE 2: SPI PROTOCOL ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 4 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Hold Operation HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 3 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 18 for Hold timing. SCK HOLD# Active Hold Active Hold Active 1264 F03.0 FIGURE 3: HOLD CONDITION WAVEFORM Write Protection The SST25VF512A provides software Write protection. The Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled. TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUSREGISTER (WRSR) INSTRUCTION WP# L L H BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed T3.0 1264 ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 5 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or TABLE 4: SOFTWARE STATUS REGISTER Bit 0 1 2 3 4:5 6 Name BUSY WEL BP0 BP1 RES AAI Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP1, BP0 are read-only bits 0 = BP1, BP0 are read/writable Default at Power-up 0 0 1 1 0 0 Read/Write R R R/W R/W N/A R Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. 7 BPL 0 R/W T4.0 1264 Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: • • • • • • • Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming reached its highest memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 6 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After power-up, BP1 and BP0 are set to 1. Block Protection Lock-Down (BPL) WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. TABLE 5: SOFTWARE STATUS REGISTER BLOCK PROTECTION1 Status Register Bit Protection Level 0 1 (1/4 Memory Array) 2 (1/2 Memory Array) 3 (Full Memory Array) BP1 0 0 1 1 BP0 0 1 0 1 Protected Memory Area None 0C000H-0FFFFH 08000H-0FFFFH 00000H-0FFFFH T5.0 1264 1. Default at power-up for BP1 and BP0 is ‘11’. Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 7 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF512A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 6. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the TABLE 6: DEVICE OPERATION INSTRUCTIONS1 Bus Cycle2 Cycle Type/Operation3,4 SIN 03H 0BH 20H 52H or D8H 60H or C7H 02H AFH 05H 50H 01H 06H 04H 90H or ABH Read (20 MHz) High-Speed-Read (33 MHz) Sector-Erase5,6 Block-Erase5,7 Chip-Erase6 Byte-Program6 Auto Address Increment (AAI) Program6,8 Read-Status-Register (RDSR) Enable-Write-Status-Register (EWSR)10 Write-Status-Register (WRSR)10 Write-Enable (WREN) Write-Disable (WRDI) Read-ID most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. 1 SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2 SIN A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 X Data 00H 3 SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z 4 SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note9 Hi-Z 5 SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note9 Hi-Z 6 SIN X SIN A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 00H SIN A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 -. ID Addr11 SIN X X DIN DIN X SOUT DOUT X Hi-Z Hi-Z Note9 DOUT12 SOUT DOUT DIN DIN Hi-Z Hi-Z Note9 X DOUT12 T6.0 1264 1. AMS = Most Significant Address AMS = A15 for SST25VF512A Address bits above the most significant bit of each density can be VIL or VIH 2. One bus cycle is eight clock periods. 3. Operation: SIN = Serial In, SOUT = Serial Out 4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) 5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH 6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. 7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH 8. To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be programmed. 9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s and Device ID output stream is continuous until terminated by a low to high transition on CE# 12. Device ID = 48H for SST25VF512A ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 8 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Read (20 MHz) The Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE# must remain active low for the duration of the Read cycle. See Figure 4 for the Read sequence. CE# MODE 3 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 SCK MODE 0 SI MSB SO 03 ADD. MSB HIGH IMPEDANCE ADD. ADD. N DOUT MSB 1264 F04.0 N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT FIGURE 4: READ SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 9 512 Kbit SPI Serial Flash SST25VF512A Data Sheet High-Speed-Read (33 MHz) The High-Speed-Read instruction supporting up to 33 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 5 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address location 07FFFFH has been read, the next output will be from address location 000000H. CE# MODE 3 SCK MODE 0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB SO 0B ADD. MSB HIGH IMPEDANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT 1264 F05.0 N+4 DOUT Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) FIGURE 5: HIGH-SPEED-READ SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 10 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The ByteProgram instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 6 for the Byte-Program sequence. CE# MODE 3 012345678 15 16 23 24 31 32 39 SCK MODE 0 SI MSB 02 ADD. MSB ADD. ADD. DIN MSB LSB SO HIGH IMPEDANCE 1264 F06.0 FIGURE 6: BYTE-PROGRAM SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 11 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A23-A0]. Following the addresses, the data is input sequentially from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the AAI program instruction is executed. The user must poll the BUSY bit in the software status register or wait TBP for the completion of each internal self-timed Byte-Program cycle. Once the device completes programming byte, the next sequential address may be program, enter the 8-bit command, AFH, followed by the data to be programmed. When the last desired byte had been programmed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the WRDI command, the user must poll the Status register to ensure the device completes programming. See Figure 7 for AAI programming sequence. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0). TBP CE# MODE 3 TBP 012345678 15 16 23 24 31 32 33 34 35 36 37 38 39 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 SCK MODE 0 SI AF A[23:16] A[15:8] A[7:0] Data Byte 1 AF Data Byte 2 TBP CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK AF Last Data Byte 04 Write Disable (WRDI) Instruction to terminate AAI Operation 05 Read Status Register (RDSR) Instruction to verify end of AAI Operation DOUT 1264 F07.0 SI SO FIGURE 7: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 12 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal selftimed Sector-Erase cycle. See Figure 8 for the SectorErase sequence. CE# MODE 3 012345678 15 16 23 24 31 SCK MODE 0 SI MSB 20 ADD. MSB ADD. ADD. SO HIGH IMPEDANCE 1264 F08.0 FIGURE 8: SECTOR-ERASE SEQUENCE Block-Erase The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H or D8H, followed by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most significant address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal selftimed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. CE# MODE 3 012345678 15 16 23 24 31 SCK MODE 0 SI MSB 52 or D8 ADD. MSB ADD. ADD. SO HIGH IMPEDANCE 1264 F09.0 FIGURE 9: BLOCK-ERASE SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 13 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 10 for the Chip-Erase sequence. CE# MODE 3 01234567 SCK MODE 0 SI MSB 60 or C7 HIGH IMPEDANCE 1264 F10.0 SO FIGURE 10: CHIP-ERASE SEQUENCE Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. ReadStatus-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 11 for the RDSR instruction sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK SI SO MODE 0 05 MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1264 F11.0 FIGURE 11: READ-STATUS-REGISTER (RDSR) SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 14 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Write-Enable (WREN) The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. CE# MODE 3 01234567 SCK MODE 0 SI MSB 06 HIGH IMPEDANCE 1264 F12.0 SO FIGURE 12: WRITE ENABLE (WREN) SEQUENCE Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE# must be driven high before the WRDI instruction is executed. CE# MODE 3 01234567 SCK MODE 0 SI MSB 04 HIGH IMPEDANCE 1264 F13.0 SO FIGURE 13: WRITE DISABLE (WRDI) SEQUENCE Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-WriteStatus-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write©2006 Silicon Storage Technology, Inc. Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. S71264-02-000 1/06 15 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-Status-Register instruction must be executed immediately after the execution of the EnableWrite-Status-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. The Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction, the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 and BP1 bit at the same time. See Table 3 for a summary description of WP# and BPL functions. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruction sequences. CE# MODE 3 01234567 MODE 3 MODE 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK MODE 0 SI MSB SO 50 MSB 01 HIGH IMPEDANCE STATUS REGISTER IN 76543210 MSB 1264 F14.0 FIGURE 14: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 16 512 Kbit SPI Serial Flash SST25VF512A Data Sheet Read-ID The Read-ID instruction identifies the device as SST25VF512A and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#. CE# MODE 3 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 SCK MODE 0 SI MSB 90 or AB 00 00 ADD1 MSB SO HIGH IMPEDANCE MSB BF Device ID BF Device ID HIGH IMPEDANCE Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1264 F15.0 FIGURE 15: READ-ID SEQUENCE ©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06 17 512 Kbit SPI Serial Flash SST25VF512A Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (