SST27SF020-70-3C-PG

256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories Data Sheet FEATURES: • Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8 • 4.5-5.5V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical) • Fast Read Access Time – 70 ns – 90 ns • Fast Byte-Program Operation – Byte-Program Time: 20 µs (typical) – Chip Program Time: 0.7 seconds (typical) for SST27SF256 1.4 seconds (typical) for SST27SF512 2.8 seconds (typical) for SST27SF010 5.6 seconds (typical) for SST27SF020 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • TTL I/O Compatibility • JEDEC Standard Byte-wide EPROM Pinouts • Packages Available – 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 28-pin PDIP for SST27SF256/512 – 32-pin PDIP for SST27SF010/020 PRODUCT DESCRIPTION The SST27SF256/512/010/020 are a 32K x8 / 64K x8 / 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST’s proprietary, high performance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12 volt power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Byte-Program, the SST27SF256/512/010/020 provide a Byte-Program time of 20 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST27SF256/512/010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27SF256/512 are offered in 32-pin PLCC, 32-pin TSOP and 28-pin PDIP packages. The , SST27SF010/020 are offered in 32-pin PDIP 32-pin PLCC , and 32-pin TSOP packages. See Figures 1, 2, and 3 for pinouts. © 2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 1 Device Operation The SST27SF256/512/010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP , and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the SST27SF256/512/010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 µA is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Byte-Program Operation The SST27SF256/512/010/020 are programmed by using an external programmer. The programming mode for SST27SF256/010/020 is activated by asserting 12V (±5%) The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet on VPP pin, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. The programming mode for SST27SF512 is activated by asserting 12V (±5%) on OE#/VPP pin, VDD = 5V (±5%), and VIL on CE# pin. These devices are programmed byte-by-byte with the desired data at the desired address using a single pulse (CE# pin low for SST27SF256/512 and PGM# pin low for SST27SF010/ 020) of 20 µs. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed. Product Identification Mode The Product Identification mode identifies the devices as the SST27SF256, SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27SF256/010/020, the programming equipment must force VH (12V±5%) on address A9 with VPP pin at VDD (5V±10%) or VSS. To activate this mode for SST27SF512, the programming equipment must force VH (12V±5%) on address A9 with OE#/VPP pin at VIL. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Tables 3, 4, and 5 for hardware operation. TABLE 1: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST27SF256 SST27SF512 SST27SF010 SST27SF020 0001H 0001H 0001H 0001H A3H A4H A5H A6H T1.1 502 Chip-Erase Operation The only way to change a data from a “0” to “1” is by electrical erase that changes every bit in the device to “1”. Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27SF256/512/010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (CE# pin low for SST27SF256/512 and PGM# pin for SST27SF010/020). In order to activate the Erase mode for SST27SF256/010/020, the 12V (±5%) is applied to VPP and A9 pins, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. In order to activate Erase mode for SST27SF512, the 12V (±5%) is applied to OE#/VPP and A9 pins, VDD = 5V (±5%), and VIL on CE# pin. All other address and data pins are “don’t care”. The falling edge of CE# (PGM# for SST27SF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figures 13, 14, and 15 for the flowcharts. Data BFH 0000H ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 2 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF256 X-Decoder SuperFlash Memory A14 - A0 Address Buffer Y-Decoder CE# OE# VPP A9 Control Logic I/O Buffers DQ7 - DQ0 502 ILL B1.1 FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF512 X-Decoder SuperFlash Memory A15 - A0 Address Buffer Y-Decoder CE# OE#/VPP A9 Control Logic I/O Buffers DQ7 - DQ0 502 ILL B2.1 FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF010/020 X-Decoder SuperFlash Memory AMS - A0 Address Buffer Y-Decoder CE# OE# A9 VPP PGM# I/O Buffers Control Logic DQ7 - DQ0 502 ILL B3.2 AMS = A17 for SST27SF020, A16 for SST27SF010 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 3 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet SST27SF256 SST27SF512 SST27SF010 SST27SF020 PGM# PGM# A14 A14 VDD VPP A12 A15 A16 VDD VPP A12 A15 A16 VDD A12 A15 VDD VPP A12 SST27SF020 SST27SF010 SST27SF512 SST27SF256 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A6 A5 A4 A3 A2 A1 A0 NC DQ0 A6 A5 A4 A3 A2 A1 A0 NC DQ0 5 6 7 8 9 10 11 12 13 SST27SF020 SST27SF010 SST27SF512 SST27SF256 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 VSS DQ1 DQ2 NC DQ3 DQ4 DQ5 A13 SST27SF256 SST27SF512 SST27SF010 SST27SF020 A8 A9 A11 NC OE# A10 CE# DQ7 DQ6 A8 A9 A11 NC OE#/VPP A10 CE# DQ7 DQ6 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 502 ILL F02c.2 32-pin PLCC Top View DQ1 DQ2 VSS NC NC A7 DQ3 DQ4 DQ5 DQ5 DQ1 DQ2 VSS DQ3 DQ4 DQ1 DQ2 VSS DQ3 DQ4 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC ©2001 Silicon Storage Technology, Inc. DQ6 DQ6 DQ5 A13 NC A7 NC A17 S71152-02-000 5/01 502 4 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet SST27SF020 SST27SF010 SST27SF512 SST27SF256 A11 A9 A8 A13 A14 A17 PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC NC VDD NC NC A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC NC VDD VPP NC NC A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SST27SF256 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 SST27SF512 SST27SF010 SST27SF020 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 Standard Pinout Top View Die Up 502 ILL F01.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM) SST27SF020 SST27SF010 SST27SF512 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27SF256 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SST27SF256 VDD A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 502 ILL F02a.1 SST27SF010 SST27SF020 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 502 ILL F02b.1 SST27SF512 VDD A14 A13 A8 A9 A11 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 28-pin PDIP Top View VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 FIGURE 3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 5 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 2: PIN DESCRIPTION Symbol AMS1-A0 DQ7-DQ0 CE# OE# OE#/VPP VPP VDD VSS NC Pin Name Address Inputs Data Input/output Chip Enable Output Enable Output Enable/VPP Power Supply for Program or Erase Power Supply Ground No Connection Unconnected pins. T2.3 502 Functions To provide memory addresses To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low For SST27SF256/010/020, to gate the data output buffers during Read operation For SST27SF512, to gate the data output buffers during Read operation and high voltage pin during Chip-Erase and programming operation For SST27SF256/010/020, high voltage pin during Chip-Erase and programming operation 12V (±5%) To provide 5.0V supply (±10%) 1. AMS = Most significant address AMS = A14 for SST27SF256, A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 6 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 3: OPERATION MODES SELECTION FOR SST27SF256 Mode Read Output Disable Byte-Program Standby Chip-Erase Program/Erase Inhibit Product Identification CE# VIL VIL VIL VIH VIL VIH VIL OE# VIL VIH VIH X VIH X VIL VPP VDD or VSS VDD or VSS VPPH VDD or VSS VPPH VPPH VDD or VSS A9 AIN X AIN X VH X VH DQ DOUT High Z DIN High Z High Z High Z Manufacturer’s ID (BFH) Device ID (A3H) Address AIN X AIN X X X A14 - A1 = VIL, A0 = VIL A14 - A1 = VIL, A0 = VIH T3.1 502 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% TABLE 4: OPERATION MODES SELECTION FOR SST27SF512 Mode Read Output Disable Program Standby Chip-Erase Program/Erase Inhibit Product Identification CE# VIL VIL VIL VIH VIL VIH VIL OE#/VPP VIL VIH VPPH X VPPH VPPH VIL A9 AIN X AIN X VH X VH DQ DOUT High Z DIN High Z High Z High Z Manufacturer’s ID (BFH) Device ID (A4H) Address AIN X AIN X X X A15 - A1 = VIL, A0 = VIL A15 - A1 = VIL, A0 = VIH T4.1 502 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% TABLE 5: OPERATION MODES SELECTION FOR SST27SF010/020 Mode Read Output Disable Program Standby Chip-Erase Program/Erase Inhibit Product Identification CE# VIL VIL VIL VIH VIL VIH VIL OE# VIL VIH VIH X VIH X VIL PGM# X X VIL X VIL X X A9 AIN X AIN X VH X VH VPP VDD or VSS VDD or VSS VPPH VDD or VSS VPPH VPPH VDD or VSS DQ DOUT High Z DIN High Z High Z High Z Manufacturer’s ID (BFH) Device ID1 Address AIN AIN AIN X X X AMS2 - A1 = VIL, A0 = VIL AMS2 - A1 = VIL, A0 = VIH T5.1 502 1. Device ID = A5H for SST27SF010 and A6H for SST27SF020 2. AMS = Most significant address AMS = A16 for SST27SF010 and A17 for SST27SF020 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 7 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (