SST27VF020-90-3C-PHE

1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash SST27VF010 / SST27VF020 SST27VF010 / 0205.0V-Read 1Mb / 2Mb (x8) MTP flash memories Preliminary Specifications FEATURES: • Organized as 128K x8 / 256K x8 • 2.7-3.6V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) – Standby Current: 2 µA (typical) • Fast Read Access Time – 70 ns (PLCC or TSOP) – 90 ns (PDIP) • Fast Byte-Program Operation – Byte-Program Time: 15 µs (typical) – Chip Program Time: 2 seconds (typical) for SST27VF010 4 seconds (typical) for SST27VF020 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • JEDEC Standard Byte-wide EPROM Pinouts • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 32-pin PDIP PRODUCT DESCRIPTION The SST27VF010/020 are 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST’s proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12V power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Byte-Program, the SST27VF010/020 provide a Byte-Program time of 15 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST27VF010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27VF010/020 are offered in 32-pin PDIP 32-lead PLCC, and 32-lead TSOP packages. See , Figures 1, 2, and 3 for pin assignments. Device Operation The SST27VF010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical Erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the SST27VF010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE-TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 2 µA is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. © 2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 Preliminary Specifications Byte-Program Operation The SST27VF010/020 are programmed by using an external programmer. The programming mode for SST27VF010/020 is activated by asserting 11.4-12.0V on VPP pin, VDD = 2.7-3.6V, VIL on CE# pin, and VIH on OE# pin. These devices are programmed byte-by-byte with the desired data at the desired address using a single pulse (PGM# pin low for SST27VF010/020) of 15 µs. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed. pins are “don’t care”. The falling edge of CE# (PGM# for SST27VF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 9 for the flowchart. Product Identification Mode The Product Identification mode identifies the devices as the SST27VF010 or SST27VF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27VF010/020, the programming equipment must force VH (11.4-12.6V) on address A9 with VPP pin at VDD (2.7-3.6V) or VSS. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. TABLE 1: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST27VF010 SST27VF020 0001H 0001H A9H AAH T1.0 1251 Chip-Erase Operation The only way to change a data from a “0” to “1” is by electrical erase that changes every bit in the device to “1”. Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27VF010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (PGM# pin for SST27VF010/020). In order to activate the Erase mode for SST27VF010/020, the 11.4-12.6V is applied to the A9 pin, 11.4-12.0V is applied to the VPP pin, VDD = 2.7-3.6V, VIL on CE# pin, and VIH on OE# pin. All other address and data FUNCTIONAL BLOCK DIAGRAM OF THE SST27VF010/020 Data BFH 0000H X-Decoder SuperFlash Memory AMS - A0 Address Buffer Y-Decoder CE# OE# A9 VPP PGM# I/O Buffers Control Logic DQ7 - DQ0 1251 B1.0 AMS = A17 for SST27VF020, A16 for SST27VF010 ©2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 2 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 Preliminary Specifications SST27VF010 SST27VF020 PGM# PGM# VDD VPP A12 A15 A16 VDD VPP A12 A15 A16 SST27VF010/020 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 SST27VF010/020 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 NC SST27VF010/020 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 1251 32-plcc P1.0 32-lead PLCC Top View DQ1 DQ2 VSS DQ3 DQ4 DQ5 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC SST27VF020 SST27VF010 A11 A9 A8 A13 A14 A17 PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1251 32-tsop P2.0 DQ6 A17 SST27VF010/020 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 Standard Pinout Top View Die Up FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) ©2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 3 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 Preliminary Specifications SST27SV010/020 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SST27VF010 SST27VF020 VDD PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 1251 32-pdip P3.0 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP ©2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 4 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 Preliminary Specifications TABLE 2: PIN DESCRIPTION Symbol AMS1-A0 DQ7-DQ0 CE# OE# VPP VDD VSS NC Pin Name Address Inputs Data Input/output Chip Enable Output Enable Power Supply for Program or Erase Power Supply Ground No Connection Unconnected pins. T2.0 1251 Functions To provide memory addresses To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low To gate the data output buffers during Read operation High voltage pin during Chip-Erase and programming operation 11.4-12.0V To provide 3.0V supply (2.7-3.6V) 1. AMS = Most significant address AMS = A16 for SST27VF010 and A17 for SST27VF020 TABLE 3: OPERATION MODES SELECTION Mode Read Output Disable Program Standby Chip-Erase Program/Erase Inhibit Product Identification CE# VIL VIL VIL VIH VIL VIH VIL OE# VIL VIH VIH X VIH X VIL PGM# X1 X VIL X VIL X X A9 AIN X AIN X VH X VH VPP VDD or VSS VDD or VSS VPPH VDD or VSS VPPH VPPH VDD or VSS DQ DOUT High Z DIN High Z High Z High Z Manufacturer’s ID (BFH) Device ID2 Address AIN AIN AIN X X X AMS3 - A1=VIL, A0=VIL AMS3 - A1=VIL, A0=VIH T3.0 1251 1. X can be VIL or VIH, but no other value. 2. Device ID = A9H for SST27VF010 and AAH for SST27VF020 3. AMS = Most significant address AMS = A16 for SST27VF010 and A17 for SST27VF020 Note: VPPH = 11.4-12.0V, VH = 11.4-12.6V ©2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 5 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (