SST30VR022-70-C-WH

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo Data Sheet FEATURES: • ROM + SRAM ROM/RAM Combo – SST30VR021: 256K x8 ROM + 128K x8 SRAM – SST30VR022: 256K x8 ROM + 256K x8 SRAM – SST30VR023: 256K x8 ROM + 32K x8 SRAM • ROM/RAM combo on a monolithic chip • Equivalent ComboMemory (Flash + SRAM): SST31LF021E for code development and pre-production • Wide Operating Voltage Range: 2.7-3.3V • Chip Access Time – SST30VR022 70 ns – SST30VR021/023 500 ns • Low Power Dissipation: – Standby: 3 µW (Typical) – Operating: 10 mW (Typical) • Fully Static Operation – No clock or refresh required • Three state Outputs • Packages Available – 32-pin TSOP (8mm x14mm) PRODUCT DESCRIPTION The SST30VR021/022/023 are ROM/RAM combo chips consisting of 2 Mbit Read Only Memory organized as 256 KBytes and Static Random Access Memory organized as 128, 256, and 32 KBytes. The device is fabricated using SST’s advanced CMOS low power process technology. The SST30VR021/022/023 has an output enable input for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and for minimizing current drain during power-down mode. The SST30VR021/022/023 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications. FUNCTIONAL BLOCK DIAGRAM RAMCS# ROMCS# OE# WE# Control Circuit RAMCS# OE# WE# Data Buffer RAM Address Buffer DQ7-DQ0 ROMCS# OE# AMS-A0 ROM Note: AMS = Most Significant Address 380 ILL B1.1 © 2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet A11 A9 A8 A13 A14 A17 RAMCS# VDD WE# A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 380 ILL F01.0 OE# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP TABLE 1: PIN DESCRIPTION Symbol AMS1-A0 Pin Name Address Inputs, for ROM: AMS = A17, for RAM: AMS =A16 for SST30VR021 A17 for SST30VR022 A14 for SST30VR023 Write Enable Input Output Enable RAM Enable Input ROM Enable Input Data Input/Output Power Supply Ground T1.2 380 WE# OE# RAMCS# ROMCS# DQ7-DQ0 VDD VSS 1. AMS = Most significant address ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 2 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Voltage on Any Pin Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C OPERATING RANGE Range Commercial Extended Ambient Temp 0°C to +70°C VDD 2.7-3.3V 2.7-3.3V -20°C to +85°C OF AC CONDITIONS TEST Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . 0-VDD Input & Output Timing Reference Levels . . . . . . . VDD/2 Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 500 ns TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min 2.7 0 2.4 -0.3 Max 3.3 0 VDD + 0.5 0.3 Units V V V V T2.0 380 TABLE 3: DC OPERATING CHARACTERISTICS VDD = 3.0 ± 0.3V Symbol IDD1 IDD2 ISB ILI ILO VOL VOH Parameter ROM Operating Supply Current RAM Operating Supply Current Standby VDD Current Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage 2.2 -1 -1 Min Max 4.0+1.1(f)1 2.5+1(f)1 10 1 1 0.4 Units mA mA µA µA µA V V Test Conditions ROMCS#=VIL, RAMCS#=VIH, VIN=VIH or VIL, II/O=Opens ROMCS#=VIH, RAMCS#=VIL, II/O=Opens ROMCS#≥VDD-0.2V, RAMCS#≥VDD-0.2V VIN≥VDD-0.2V or VIN ≤0.2V VIN=VSS to VDD ROMCS#=RAMCS#=VIH or OE#=VIH or WE#=VIL, VI/O=VSS to VDD IOL = 1.0 mA IOH = -0.5 mA T3.3 380 1. f = Frequency of operation (MHz) = 1/cycle time ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 3 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet TABLE 4: CAPACITANCE Parameter CI/O1 CIN 1 (Ta = 25°C, f=1 Mhz) Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 8 pF 6 pF T4.1 380 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 380 ILL F08.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are