SST31LF021E-70-4E-WH

2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E SST31LF021 / 021E2 Mb Flash (x8) + 1 Mb SRAM (x8) Monolithic ComboMemories Data Sheet FEATURES: • Monolithic Flash + SRAM ComboMemory – SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM • Single 3.0-3.6V Read and Write Operations • Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 10 mA (typical) for Flash and 20 mA (typical) for SRAM Read – Standby Current: 10 µA (typical) • Flash Sector-Erase Capability – Uniform 4 KByte sectors • Latched Address and Data for Flash • Fast Read Access Times: – SST31LF021 Flash: 70 ns SRAM: 70 ns – SST31LF021E Flash: 300 ns SRAM: 300 ns • Flash Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Bank-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Bank Rewrite Time: 4 seconds (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Package Available – 32-lead TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST31LF021/021E devices are a 256K x8 CMOS flash memory bank combined with a 128K x8 or 32K x8 CMOS SRAM memory bank manufactured with SST’s proprietary, high performance SuperFlash technology. Two pinout standards are available for these devices. The SST31LF021 conform to JEDEC standard flash pinouts and the SST31LF021E conforms to standard EPROM pinouts. The SST31LF021/021E devices write (SRAM or flash) with a 3.0-3.6V power supply. The monolithic SST31LF021/021E devices conform to Software Data Protect (SDP) commands for x8 EEPROMs. Featuring high performance Byte-Program, the flash memory bank provides a maximum Byte-Program time of 20 µsec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 4 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LF021/ 021E devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LF021/ 021E devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST31LF021/021E operate as two independent memory banks with respective bank enable signals. The SRAM and flash memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST31LF021/021E provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Byte-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus © 2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E Data Sheet requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST31LF021/021E devices are suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LF021/021E devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LF021/021E inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; therefore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST31LF021/021E devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LF021/021E devices are offered in 32-lead TSOP packages. See Figure 1 for the pinouts. SRAM Operation With BES# low and BEF# high, the SST31LF021/021E operate as a 128K x8 or 32K x8 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LF021/021E are controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 2 for the Read cycle timing diagram. SRAM Write The SRAM Write operation of the SST31LF021/021E are controlled by WE# and BES#, both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge to the first rising edge of BES# and WE#. See Figure 3 for the Write cycle timing diagram. Flash Operation With BEF# active, the SST31LF021/021E operate as a 256K x8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. Device Operation The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be executed in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared; which minimizes power consumption and area. The device goes into standby when both bank enables are raised to VIHC. Flash Read The Read operation of the SST31LF021/021E devices are controlled by BEF# and OE#, both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 4 for the Read cycle timing diagram. ©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 2 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E Data Sheet Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LF021/021E. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Bank-Erase Operation The SST31LF021/021E flash memory bank provides a Bank-Erase operation, which allows the user to erase the entire flash memory bank array to the ‘1’s state. This is useful when the entire bank must be quickly erased. The BankErase operation is initiated by executing a six-byte Software Data Protection command sequence with Bank-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read operations are Toggle Bit and Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 19 for the flowchart. Any SDP commands loaded during the Bank-Erase operation will be ignored. Flash Byte-Program Operation The flash memory bank of the SST31LF021/021E devices are programmed on a byte-by-byte basis. Before the Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and BEF# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Write Operation Status Detection The SST31LF021/021E flash memory bank provides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Sector-Erase Operation The Sector-Erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a sixbyte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A17-A12 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any SDP commands loaded during the Sector-Erase operation will be ignored. Flash Data# Polling (DQ7) When the SST31LF021/021E flash memory bank is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector or Bank-Erase, the Data# Polling is valid S71137-03-000 10/01 392 ©2001 Silicon Storage Technology, Inc. 3 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E Data Sheet after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 17 for a flowchart. Concurrent Read and Write Operations The SST31LF021/021E provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. SST does not recommend that both bank enables, BEF# and BES#, be simultaneously asserted. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sector or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 17 for a flowchart. Flash Memory Data Protection The SST31LF021/021E flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Product Identification Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. The Product Identification mode identifies the devices as either SST31LF021 or SST31LF021E and the manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware device ID Read operation is typically used by a programmer to identify the correct algorithm for the SST31LF021/021E flash memory banks. Users may wish to use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 18 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST31LF021 SST31LF021E 0001H 0001H 18H 19H T1.4 392 Flash Software Data Protection (SDP) The SST31LF021/021E provide the JEDEC approved Software Data Protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LF021/021E devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the Read mode, within TRC. Data BFH 0000H Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an ©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 4 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E Data Sheet internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 18 for a flowchart. Design Considerations SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. FUNCTIONAL BLOCK DIAGRAM Address Buffers SRAM AMS - A0 BES# BEF# OE# WE# Control Logic I/O Buffers DQ7 - DQ0 Address Buffers & Latches SuperFlash Memory 392 ILL B1.2 Note: AMS = Most Significant Address SST31LF021E A11 A9 A8 A13 A14 A17 BES# VDD WE# A16 A15 A12 A7 A6 A5 A4 SST31LF021 A11 A9 A8 A13 A14 A17 WE# VDD BES# A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SST31LF021 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 392 ILL F01.3 SST31LF021E OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 Standard Pinout Top View Die Up OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) ©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 5 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E Data Sheet TABLE 2: PIN DESCRIPTION Symbol AMS1-A0 Pin Name Address Inputs Functions To provide memory addresses. During flash Sector-Erase, A17-A12 address lines will select the sector. A17-A0 to provide flash address A16-A0 to provide SST31LF021/021E SRAM addresses To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. To activate the Flash memory bank when BEF# is low. To gate the data output buffers. To control the Write operations. 3.0-3.6V Power Supply T2.3 392 DQ7-DQ0 Data Input/Output BES# BEF# OE# WE# VDD VSS SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground 1. AMS = Most significant address TABLE 3: OPERATION MODES SELECTION Mode Flash Read Program Erase SRAM Read Write Standby Flash Write Inhibit VIL VIL VIHC X X X Product Identification Hardware Mode Software Mode X X VIL VIL VIL VIL VIH VIH VH AIN Manufacturer’s ID (BFH) Device ID2 ID Code A17-A1=VIL, A0=VIL A17-A1=VIL, A0=VIH See Table 4 T3.4 392 BES# X1 X X BEF# VIL VIL VIL OE# VIL VIH VIH WE# VIH VIL VIL A9 AIN AIN X DQ DOUT DIN X Address AIN AIN Sector address, XXH for Bank-Erase AIN AIN X X X X VIH VIH VIHC X X VIH VIL X X VIL X X VIH VIL X X VIH X AIN AIN X X X X DOUT DIN High Z High Z / DOUT High Z / DOUT High Z / DOUT 1. X can be VIL or VIH, but no other value. 2. Device ID 18H for SST31LF021, 19H for SST31LF021E. ©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 6 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence Byte-Program Sector-Erase Bank-Erase Software ID Exit 1. 2. 3. 4. 5. 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H Data AAH AAH AAH AAH AAH 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data A0H 80H 80H 90H F0H 4th Bus Write Cycle Addr1 BA2 5555H 5555H Data Data AAH AAH 5th Bus Write Cycle Addr1 2AAAH 2AAAH Data 55H 55H 6th Bus Write Cycle Addr1 SAX3 5555H Data 30H 10H Software ID Entry4,5 5555H T4.4 392 Address format A14-A0 (Hex),Address A15, A16, and A17 can be VIL or VIH, but no other value, for the Command sequence. BA = Program Byte address SAX for Sector-Erase; uses A17-A12 address lines The device does not remain in Software Product ID mode if powered down. With A17-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST31LF021 Device ID = 18H, is read with A0 = 1, SST31LF021E Device ID = 19H, is read with A0 = 1 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (