Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
SST32HF64A1 / 64B164Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM (x16) MCP ComboMemories
Preliminary Specifications
FEATURES:
• ComboMemories organized as: – SST32HF64A2: 4M x16 Flash + 1024K x16 PSRAM • Single 2.7-3.3V Read and Write Operations • Concurrent Operation – Read from or Write to PSRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) for Flash or PSRAM Read – Standby Current: 60 µA (typical) • Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks • Erase-Suspend/Erase-Resume Capabilities • Security-ID Feature – SST: 128 bits; User: 128 bits • Fast Read Access Times: – Flash: 70 ns – PSRAM: 70 ns • Hardware Block-Protection/WP# Input Pin – Top Block-Protection (top 32 KWord) for SST32HF64A2 • Latched Address and Data for Flash • Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Package Available – 56-ball LFBGA (8mm x 10mm x 1.4mm) – 64-ball LFBGA (8mm x 10mm x 1.4mm) • All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF64A2 ComboMemory device integrates a CMOS flash memory bank with a CMOS PseudoSRAM (PSRAM) memory bank in a Multi-Chip Package (MCP), manufactured with SST proprietary, high-performance SuperFlash technology. Featuring high-performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 µsec. To protect against inadvertent flash write, the SST32HF64A2 device contains on-chip hardware and software data protection schemes. The SST32HF64A2 device offers a guaranteed endurance of 10,000 cycles, and data retention greater than 100 years. The SST32HF64A2 device consists of two independent memory banks, each with enable signals. The flash and PSRAM memory banks are superimposed in the same memory address space, and both banks share common address lines, data lines, WE# and OE#. The memory bank is selected using the memory bank enable signals. The PSRAM bank enable signal, BES1#, selects the PSRAM bank. The flash memory bank enable signal,
© 2006 Silicon Storage Technology, Inc. S71299-02-000 11/06 1
BEF#, selects the flash memory bank. The WE# signal is used with the Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HF64A2 provides the added functionality of being able to simultaneously read from, or write to, the PSRAM bank while erasing or programming in the flash memory bank. The PSRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus required. Once the internally controlled Erase or Program cycle in the flash bank commences, the PSRAM bank can be accessed for Read or Write.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications The SST32HF64A2 device is suited for applications that use both flash memory and PSRAM memory to store code or data, and is ideal for systems requiring low power and small form factor. The SST32HF64A2 significantly improves performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. Concurrent Read/Write State Table
Flash Program/Erase Program/Erase PSRAM Read Write
The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress.
Flash Read Operation
The Read operation of the SST32HF64A2 is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 7 for further details.
Device Operation
The SST32HF64A2 uses BES1#, BES2 and BEF# to control operation of either the flash or the PSRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low and BES2 is high, the PSRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and PSRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low.
Flash Word-Program Operation
The flash memory bank of the SST32HF64A2 is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. 1. Load the three-byte sequence for Software Data Protection. 2. Load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. 3. Initiate the internal Program operation after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 10 µs. See Figures 8 and 9 for WE# and BEF# controlled Program operation timing diagrams, and Figure 23 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. During the command sequence, WP# should be statically held high or low. Any SDP commands loaded during the internal Program operation will be ignored.
Concurrent Read/Write Operation
The SST32HF64A2 provides the unique benefit of being able to read from or write to PSRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from PSRAM, while altering the data in flash. See Figure 28 for a flowchart. The following table lists all valid states.
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications
Flash Sector/Block-Erase Operation
The SST32HF64A2 offers both Sector-Erase and BlockErase operations. The Flash Sector/Block-Erase operation erases the device on a sector-by-sector (or block-by-block) basis. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. Initiate the Sector-Erase operation by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The address lines AMS-A11 are used to determine the sector address. Initiate the Block-Erase operation by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The address lines AMS-A15 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. Erase operations begin after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 13 and 14 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored, WP# should be statically held high or low.
Flash Chip-Erase Operation
The SST32HF64A2 provides a Chip-Erase operation, which allows the user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be quickly erased. Initiate the Chip-Erase operation executing a six- byte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 11 for timing diagram, and Figure 27 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF64A2 provides two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. To prevent spurious rejection, in the event of an erroneous result, the software routine must include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation allowing data to be read from any memory location, or programed to any sector/ block that is not suspended for an Erase operation. Execute the operation by issuing a one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume the Sector-Erase or Block-Erase operation which has been suspended, the system must issue the Erase Resume command. Execute the operation by issuing a one byte command sequence with Erase-Resume command (30H) at any address in the last Byte sequence.
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications
Flash Data# Polling (DQ7)
When the SST32HF64A2 flash memory banks are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is complete, DQ7 will produce true data. However, even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is complete, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 10 for Data# Polling timing diagram and Figure 24 for a flowchart.
TABLE 1: Write Operation Status
Status
Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase-Suspended Sector/Block Read from Non- Erase-Suspended Sector/Block Program
DQ7
DQ7# 0 1
DQ6
Toggle Toggle 1
DQ2
No Toggle Toggle Toggle
Data
Data
Data
DQ7#
Toggle
N/A
T1.0 1299
Note: DQ7 and DQ2 require a valid address when reading status information.
Flash Memory Data Protection
The SST32HF64A2 flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 bit will alternate between ‘1’ and ‘0’. When the internal Program or Erase operation is complete, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If a Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which is used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of Write operation. See Figure 11 for Toggle Bit timing diagram and Figure 24 for a flowchart.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the flash Write operation. This prevents inadvertent writes during power-up or power-down.
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications
Hardware Block Protection
The SST32HF64A2 supports top hardware block protection, which protects the top 32 KWord block of the device. The Boot Block address ranges are described in Table 2. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. TABLE 2: Boot Block Address Ranges
Product Top Boot Block SST32HF64A2 3F8000H-3FFFFFH
T2.0 1299
PSRAM Deep Power-down Mode
The PSRAM Deep Power-down Mode is used to lower the power consumption of the PSRAM in the SST32HF64A2. Deep Power-down occurs 1 µs after being enabled by driving BES2 low. Normal operation occurs 500 µs after driving BES2 high. In Deep Power-down mode, PSRAM data is lost. See Figure 22 for the state diagram.
PSRAM Read
The PSRAM Read operation of the SST32HF64A2 is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 4, for further details.
Address Range
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 18). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.
PSRAM Write
The PSRAM Write operation of the SST32HF64A2 is controlled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the PSRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES1# or WE#, whichever occurs first. The write time is measured from the last falling edge of BES1# or WE# to the first rising edge of BES1# or WE#. Refer to the Write cycle timing diagrams, Figures 5 and 6, for further details.
Flash Software Data Protection (SDP)
The SST32HF64A2 provides the JEDEC approved software data protection scheme for all flash memory bank data-alteration operations, i.e., Program and Erase. Any Program operation requires a three-byte sequence series. Using the three byte-load sequence to initiate the Program operation, provides optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires a six-byte load sequence. The SST32HF64A2 devices are shipped with the software data protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence.
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications
Product Identification
The Product Identification mode identifies the device as the SST32HF64A2 and manufacturer as SST. This mode is accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and PSRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 5 and 6 for software operation, Figure 15 for the software ID entry and read timing diagram and Figure 25 for the ID entry command sequence flowchart. TABLE 3: Product Identification
Address Manufacturer’s ID Device ID SST32HF64A2 0001H 236CH
T3.0 1299
gram Lock-Out. This disables any future corruption of this space. Regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin.
Data BFH
0000H
Product Identification Mode Exit/Reset
To return to the standard read mode, the Software Product Identification mode must be exited. Exit by issuing the Exit ID command sequence which returns the device to the Read operation. However, the software reset command is ignored during an internal Program or Erase operation. This command may also be used to reset the device to Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 6 for software command codes, Figure 16 for timing waveform and Figure 25 for a flowchart.
Security ID
The SST32HF64A2 device offers a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired. Use the Security ID Word-Program to program the user segment of the Security ID. To detect end-of-write for the SEC ID, read the toggle bits, not Data# Polling. Once this is complete, the Sec ID is locked using the User Sec ID Pro-
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
PSRAM
UBS# LBS# BES1# BES2 BEF# OE#1 WE#1 WP# RESET#
Control Logic I/O Buffers
AMS-A0
DQ15 - DQ8 DQ7 - DQ0
Address Buffers & Latches
SuperFlash Memory
Note: 1. For LS package only: WE# = WEF# and/or WES# OE # = OEF# and/or OES#
1299 B1.0
FIGURE 1: Functional Block Diagram
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications
PIN DESCRIPTION
TOP VIEW (balls facing down)
8
NC A20 A16 A11 A8 A15 A10 A21 A14 A9 A13
7 6
WEF# NC
A12 VSSF NC
NC
DQ15 WES# DQ14 DQ7 DQ13 DQ6 DQ4 DQ5 DQ12 BES2 VDDS VDDF DQ10 DQ2 DQ3 DQ9 DQ8 DQ0 DQ1
5 4 3
LBS# UBS# OES# VSSS RST# NC WP# NC A19 DQ11
2 1
NC
A18 NC
A17 A5
A7 A4
A6 A0
A3
A2
A1 BES1# NC
BEF# VSSF OEF# NC
ABCDEFGHJK
1299 64-lfbga L2S P2.0
FIGURE 2: Pin Assignments for 64-ball LFBGA (8mm x 10mm)
TOP VIEW (balls facing down)
8 7
A11 A15 A12 A19 A21 A13 A9 NC A14 A10 A16 NC VSS NC DQ15 DQ7 DQ14 DQ6 DQ13 DQ12 DQ5 DQ4 VDDS NC DQ3 VDDF DQ11 A17 A4 A1 DQ1 DQ9 DQ10 DQ2 VSS OE# DQ0 DQ8 A0 BEF# BES1#
6
A8
5
WE# BES2 A20
4
WP# RST# NC
3
LBS# UBS# A18
2
A7 A6 A3 A5 A2
1
ABCDEFGHJK
1299 56-lfbga L1S P3.0
FIGURE 3: Pin Assignments for 56-ball LFBGA (8mm x 10mm)
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications TABLE 4: Pin Description
Symbol AMS1 to A0 DQ15-DQ0 Pin Name Address Inputs Data Inputs/Outputs Functions To provide flash address, A21-A0. To provide PSRAM address, A19-A0 To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high. To activate the Flash memory bank when BEF# is low To activate the PSRAM memory deep power-down mode when BES2 is VIL To gate the data output buffers for Flash only To gate the data output buffers for PSRAM only To control the Write operations for Flash only To control the Write operations for PSRAM only To gate the data output buffers To control the Write operations To enable DQ15-DQ8 To enable DQ7-DQ0 To protect and unprotect sectors from Erase or Program operation To Reset and return the device to Read mode Flash only2 PSRAM only2 2.7-3.3V Power Supply to Flash only 2.7-3.3V Power Supply to PSRAM only Unconnected pins
T4.0 1299
AMSS1 to A0 Address Inputs
BEF# BES1# BES2 OEF#2 OES#2 WEF#2 WES#2 OE# WE# UBS# LBS# WP# RST# VSSF2 VSSS VSS
2
Flash Memory Bank Enable PSRAM Deep Power-down Enable Output Enable Output Enable Write Enable Write Enable Output Enable Write Enable Upper Byte Control (PSRAM) Lower Byte Control (PSRAM) Write Protect Reset Ground Ground Ground Power Supply (Flash) Power Supply (PSRAM) No Connection
PSRAM Memory Bank Enable To activate the PSRAM memory bank when BES1# is low
VDDF VDDS
NC
1. AMS = Most Significant Flash Address AMSS = Most Significant PSRAM Address 2. For L2S package only
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications TABLE 5: Operational Modes Selection1
Mode Full Standby PSRAM Deep Power-down4 Output Disable Flash Read Flash Write Flash Erase PSRAM Read BEF#2 VIH VIH VIH VIL VIL VIL VIL VIH BES1#2 VIH VIL VIL VIH VIH VIH VIH VIL BES2 VIH VIL VIH VIH VIH VIH VIH VIH OE#3 X X VIH VIH VIL VIH VIH VIL WE#3 X X VIH VIH VIH VIL VIL VIH LBS# X X X X X X X VIL VIH VIL PSRAM Write VIH VIL VIH X VIL VIL VIH VIL Product Identification5 VIL VIH VIH VIL VIH X UBS# X X X X X X X VIL VIL VIH VIL VIL VIH X DQ7-0 HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT HIGH-Z DOUT DIN HIGH-Z DIN DQ15-8 HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT DOUT HIGH-Z DIN DIN HIGH-Z
Manufacturer’s ID6 Device ID6
T5.0 1299
1. X can be VIL or VIH, but no other value. 2. For SST32HF64A2, to avoid bus contention do not apply BEF# = VIL and BES1# = VIL at the same time 3. OE# = OEF# and OES# WE# = WEF# and WES# 4. In PSRAM Deep power-down, PSRAM data is lost. 5. Software mode only 6. With A21-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0, SST32HF64A2 Device ID = 236CH, is read with A0=1.
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications TABLE 6: Software Command Sequence
Command Sequence
Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5
1st Bus Write Cycle Addr1 555H 555H 555H 555H XXXXH XXXXH 555H 555H 555H 555H 555H XXH Data2 AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH F0H
2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH Data2 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 555H 555H 555H 555H Data2 A0H 80H 80H 80H
4th Bus Write Cycle Addr1 WA3 555H 555H 555H Data2 Data AAH AAH AAH
5th Bus Write Cycle Addr1 2AAH 2AAH 2AAH Data2 55H 55H 55H
6th Bus Write Cycle Addr1 SAX4 BAX
4
Data2 50H 30H 10H
555H
2AAH 2AAH 2AAH 2AAH 2AAH
55H 55H 55H 55H 55H
555H 555H 555H 555H 555H
88H A5H 85H 90H F0H WA6 XXH6 Data 0000H
User Security ID Word-Program User Security ID Program Lock-Out Software ID Entry7,8 Software ID /Sec ID Exit Exit9,10
Software ID Exit9,10 /Sec ID Exit
T6.0 1299
1. Address format A11-A0 (Hex). Addresses A12-A21 can be VIL or VIH, but no other value, for Command sequence for SST32HF64A2. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A21 for SST32HF64A2. 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000010H to 000017H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST32HF64A2 Device ID = 236CH, is read with A0=1. AMS = Most significant address AMS = A21 for SST32HF64A2. 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
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Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF64A2
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (
