SST34HF162C

16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C SST34HF162C16Mb Dual-Bank Flash + 2/4 Mb SRAM MCP ComboMemory Preliminary Specifications FEATURES: • Flash Organization: 1M x16 – 16 Mbit: 12 Mbit + 4 Mbit • Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash • SRAM Organization: – 2 Mbit:128K x16 – 4 Mbit: 256K x16 • Single 2.7-3.3V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: (typical values @ 5 MHz) – Active Current: Flash 10 mA (typical) SRAM 6 mA (typical) – Standby Current: 10 µA (typical) • Sector-Erase Capability – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Read Access Time – Flash: 70 ns – SRAM: 70 ns • Erase-Suspend / Erase-Resume Capabilities • Latched Address and Data • Fast Erase and Word-Program (typical): – Sector-Erase Time: 18 ms – Block-Erase Time: 18 ms – Chip-Erase Time: 35 ms – Program Time: 7 µs • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Packages Available – 48-ball LBGA (10mm x 12mm) PRODUCT DESCRIPTION The SST34HF162C/164C ComboMemory devices integrate a 1M x16 CMOS flash memory bank with either 128K x16 or 256K x16 CMOS SRAM memory bank in a multichip package (MCP). These devices are fabricated using SST’s proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF162C/164C devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF162C/164C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Program time of 7 µsec. The entire flash memory bank can be erased and programmed word-by-word in 4 seconds (typically) for the SST34HF162C/164C, when using interface features such as Toggle Bit or Data# Polling © 2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 1 to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF162C/164C devices contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES#, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. See Figure 1 for memory organization. Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF162C/ 164C are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 2 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications Device Operation The SST34HF162C/164C use BES# and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES# is low the SRAM is activated for Read and Write operation. BEF# and BES# cannot be at low level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES# bank enables are raised to VIHC (Logic High) or when BEF# is high. Flash Program Operation These devices are programmed on a word-by-word basis. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 µs. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Concurrent Read/Write Operation The SST34HF162C/164C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Flash Sector- /Block-Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or SectorErase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 12 and 13 for timing waveforms. Flash Read Operation The Read operation of the SST34HF162C/164C is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 2 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications Flash Chip-Erase Operation The SST34HF162C/164C provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the “1” state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 5 for the command sequence, Figure 11 for timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Data# Polling (DQ7) When the device is in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling (DQ7) timing diagram and Figure 19 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 19 for a flowchart. TABLE 1: WRITE OPERATION STATUS Status Normal Operation Standard Program Standard Erase DQ7 DQ7# 0 DQ6 Toggle Toggle DQ2 No Toggle Toggle Flash Erase-Suspend/-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the one-byte sequence. Flash Write Operation Status Detection The SST34HF162C/164C provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to pre©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 3 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications TABLE 1: WRITE OPERATION STATUS Status EraseSuspend Mode Read From Erase Suspended Sector/ Block Read From Non-Erase Suspended Sector/ Block Program DQ7 1 DQ6 1 DQ2 Toggle Product Identification The Product Identification mode identifies the device as SST34HF162C or SST34HF164C and the manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 4 and 5 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 20 for the ID Entry command sequence flowchart. TABLE 2: PRODUCT IDENTIFICATION ADDRESS Manufacturer’s ID Device ID SST34HF162C/164C BK0001H 734BH T2.1 1269 Data Data Data DQ7# Toggle No Toggle T1.0 1269 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. Data Protection The SST34HF162C/164C provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST34HF162C/164C provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF162C/164C are shipped with the Software Data Protection permanently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 are “Don’t Care” during any SDP command sequence. DATA 00BFH BK0000H Note: BK = Bank Address (A19-A18) Product Identification Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 5 for software command codes, Figure 15 for timing waveform and Figure 20 for a flowchart. ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 4 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications SRAM Operation With BES# low and BEF# high, the SST34HF162C/164C operate as either 128K x16 or 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST34HF162C/164C SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 4 for SRAM Read and Write data byte control modes of operation. SRAM Read The SRAM Read operation of the SST34HF162C/164C is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. SRAM Write The SRAM Write operation of the SST34HF162C/164C is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE# whichever occurs first. The write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. FUNCTIONAL BLOCK DIAGRAM AMSF1- A0 AMSS2- A0 Address Buffers SuperFlash Memory (Bank 1) BEF# LBS# UBS# WE# OE# BES# SuperFlash Memory (Bank 2) Control Logic I/O Buffers DQ15 - DQ0 Address Buffers 2/4 Mbit SRAM 1269 B1.1 Notes: 1. AMSF = Most significant flash address AMSF = A19 for SST34HF162C/164C 2. AMSS = Most significant SRAM address AMSS = A16 for SST34HF162C and A17 for SST34HF164C ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 5 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications 32 KWord Blocks; 2 KWord Sectors FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 02000H 01FFFH 00000H Block 31 Block 30 Block 29 Bank 2 Bank 1 1269 F01.0 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 FIGURE 1: DUAL-BANK MEMORY ORGANIZATION ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 6 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications TOP VIEW (balls facing down) S ST34HF162C/164C 6 5 4 3 2 1 BES# VSS DQ1 A10 DQ5 DQ2 OE# DQ7 DQ4 A11 A13 A8 A5 A1 A0 DQ0 DQ8 A2 A3 A6 A4 A7 A18 A19 NC NC A9 A14 A15 DQ3 DQ12 A12 LBS# DQ6 DQ15 WE# VDDS A16 VSS DQ9 DQ11 DQ13 DQ14 ABCDEFGH FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM) TABLE 3: PIN DESCRIPTION Symbol Pin Name Functions To provide flash address, A19-A0. To provide SRAM address, AMSS-A0 AMSS1 to A0 Address Inputs DQ15-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE#, BES#, and BEF# are high. To activate the Flash memory bank when BEF# is low To activate the SRAM memory bank when BES# is low To gate the data output buffers To control the Write operations To enable DQ15-DQ8 To enable DQ7-DQ0 2.7-3.3V Power Supply to Flash only 2.7-3.3V Power Supply to SRAM only Unconnected pins T3.1 1269 BEF# BES# OE# WE# UBS# LBS# VSS Flash Memory Bank Enable SRAM Memory Bank Enable Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Ground Power Supply (Flash) Power Supply (SRAM) No Connection VDDF VDDS NC 1. AMS = Most Significant Address AMS = A16 for SST34HF162C and A17 for SST34HF164C ©2004 Silicon Storage Technology, Inc. 1269 48-lbga P1.1 A17 UBS# BEF# DQ10 VDDF S71269-01-000 9/04 7 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications TABLE 4: OPERATIONAL MODES SELECTION FOR SRAM Mode Full Standby Output Disable BEF#1 VIH VIH VIL Flash Read Flash Write Flash Erase SRAM Read VIL VIL VIL VIH BES#1,2 VIH X VIL VIL VIH X VIH X VIH X VIH X VIL VIL VIH VIL VIH VIL SRAM Write VIH VIL X VIL VIL VIH VIL Product Identification3 1. 2. 3. 4. OE#2 X X VIH X VIH VIL VIH VIH WE#2 X X VIH X VIH VIH VIL VIL LBS#2 X X X VIH X X X X UBS#2 X X X VIH X X X X VIL VIL VIH VIL VIL VIH X DQ15-0 HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT HIGH-Z DOUT DIN HIGH-Z DIN HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT DOUT HIGH-Z DIN DIN HIGH-Z DQ15-8 HIGH-Z HIGH-Z HIGH-Z DQ15-8=HIGH-Z DQ15-8=HIGH-Z X DOUT DOUT HIGH-Z DIN DIN HIGH-Z VIL VIH VIL VIH X Manufacturer’s ID4 Device ID4 T4.1 1269 Do not apply BEF# = VIL and BES# = VIL at the same time X can be VIL or VIH, but no other value. Software mode only With A19-A18 = VIL; SST Manufacturer’s ID = BFH, is read with A0=0, SST34HF162C/164C Device ID = 734BH, is read with A0=1 ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 8 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C Preliminary Specifications TABLE 5: SOFTWARE COMMAND SEQUENCE Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Software ID Entry5 1st Bus Write Cycle Addr1 555H 555H 555H 555H XXXXH XXXXH 555H 555H XXH 2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH 3rd Bus Write Cycle Addr1 555H 555H 555H 555H 4th Bus Write Cycle Addr1 WA3 555H 555H 555H 5th Bus Write Cycle Addr1 2AAH 2AAH 2AAH 6th Bus Write Cycle Addr1 SAX4 BAX 4 Data2 AAH AAH AAH AAH B0H 30H AAH AAH F0H Data2 55H 55H 55H 55H Data2 A0H 80H 80H 80H Data2 Data AAH AAH AAH Data2 55H 55H 55H Data2 30H 50H 10H 555H 2AAH 2AAH 55H 55H BKX6 555H 555H 90H F0H Software ID Exit Software ID Exit 1. 2. 3. 4. T5.0 1269 Address format A11-A0 (Hex), Addresses A19-A12 can be VIL or VIH, but no other value, for the command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence WA = Program word address SAX for Sector-Erase; uses A19-A10 address lines BAX for Block-Erase; uses A19-A15 address lines 5. The device does not remain in Software Product Identification mode if powered down. 6. A19 and A18 = VIL Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (