SST37VF040-90-3C-NH

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories Data Sheet FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • 2.7-3.6V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 10 mA (typical) – Standby Current: 2 µA (typical) • Fast Read Access Time: – 70 ns – 90 ns • Latched Address and Data • Fast Byte-Program Operation: – Byte-Program Time: 10 µs (typical) – Chip Program Time: 0.6 seconds (typical) for SST37VF512 1.2 seconds (typical) for SST37VF010 2.4 seconds (typical) for SST37VF020 4.8 seconds (typical) for SST37VF040 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • CMOS I/O Compatibility • JEDEC Standard Byte-wide Flash EEPROM Pinouts • Packages Available – 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 32-pin PDIP PRODUCT DESCRIPTION The SST37VF512/010/020/040 devices are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST37VF512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST37VF512/010/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories. Featuring high performance Byte-Program, the SST37VF512/010/020/040 provide a typical Byte-Program time of 10 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST37VF512/010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST37VF512/010/020/040 are offered in 32-pin PLCC, TSOP and PDIP packages. See Figures 1, , 2, and 3 for pinouts. Device Operation The SST37VF512/010/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. It is functionally (Read) and pin compatible with industry standard flash products.The device supports electrical Erase operation via an external programmer. Read The Read operation of the SST37VF512/010/020/040 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming the CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a standby current of only 10 µA (typical) is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is VIH. Refer to Figure 4 for the timing diagram. © 2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Byte-Program Operation The SST37VF512/010/020/040 are programmed by using an external programmer. The programming mode is activated by asserting 12V (±5%) on OE# pin and VIL on CE# pin. The device is programmed using a single pulse (WE# pin low) of 10 µs per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-bybyte until the entire chip has been programmed. Refer to Figure 10 for the flowchart and Figure 6 for the timing diagram. Product Identification Mode The Product Identification mode identifies the devices as SST37VF512, SST37VF010, SST37VF020, and SST37VF040 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (12V±5%) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. TABLE 1: PRODUCT IDENTIFICATION Chip-Erase Operation The only way to change a data from a “0” to “1” is by electrical erase that changes every bit in the device to “1”. The SST37VF512/010/020/040 use an electrical Chip-Erase operation. The entire chip can be erased in 100 ms (WE# pin low). In order to activate erase mode, the 12V (±5%) is applied to OE# and A9 pins while CE# is low. All other address and data pins are “don’t care”. The falling edge of WE# will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 9 for the flowchart and Figure 5 for the timing diagram. Manufacturer’s ID Device ID SST37VF512 SST37VF010 SST37VF020 SST37VF040 Address 0000H 0001H 0001H 0001H 0001H Data BFH C4H C5H C6H C2H T1.2 397 Design Considerations The SST37VF512/010/020/040 should have a 0.1µF ceramic high frequency, low inductance capacitor connected between VDD and GND. This capacitor should be placed as close to the package terminals as possible. OE# and A9 must remain stable at VH for the entire duration of an Erase operation. OE# must remain stable at VH for the entire duration of the Program operation. FUNCTIONAL BLOCK DIAGRAM X-Decoder SuperFlash Memory Memory Address Address Buffer Y-Decoder CE# OE# A9 WE# Control Logic I/O Buffers DQ7 - DQ0 397 ILL B1.1 ©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397 2 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet SST37VF512 SST37VF010 SST37VF020 SST37VF040 WE# WE# WE# WE# VDD A12 A15 A16 A18 VDD A12 A15 A16 VDD A12 A15 A16 NC VDD A12 A15 NC NC SST37VF040 SST37VF020 SST37VF010 SST37VF512 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 NC SST37VF512 SST37VF010 SST37VF020 SST37VF040 5 6 7 8 9 10 11 12 13 SST37VF040 SST37VF020 SST37VF010 SST37VF512 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 NC A17 NC A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 32-pin PLCC Top View 21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 397 ILL F02a.2 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ5 DQ5 DQ1 DQ2 VSS DQ3 DQ4 DQ1 DQ2 VSS DQ3 DQ4 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC SST37VF040 SST37VF020 SST37VF010 SST37VF512 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DQ6 DQ6 DQ6 SST37VF512 SST37VF010 SST37VF020 SST37VF040 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 397 ILL F01.0 Standard Pinout Top View FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM ©2001 Silicon Storage Technology, Inc. X 14MM) S71151-02-000 5/01 397 3 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet SST37VF040 SST37VF020 SST37VF010 SST37VF512 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SST37VF512 SST37VF010 SST37VF020 SST37VF040 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 397 ILL F02b.1 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP TABLE 2: PIN DESCRIPTION Symbol AMS1-A0 DQ7-DQ0 CE# WE# OE# VDD VSS NC Pin Name Address Inputs Data Input/output Chip Enable Write Enable Output Enable Power Supply Ground No Connection Unconnected pins. T2.1 397 Functions To provide memory addresses. To output data during Read cycles and receive input data during Program cycles. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To program or erase (WE# = VIL pulse during Program or Erase) To gate the data output buffers during Read operation when low To provide 3.0V supply (2.7-3.6V) 1. AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040 ©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397 4 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TABLE 3: OPERATION MODES SELECTION Mode Read Output Disable Standby Chip-Erase Byte-Program Program/Erase Inhibit Product Identification CE# VIL VIL VIH VIL VIL X X VIL WE# VIH X X VIL VIL VIH X VIH A9 AIN X X VH AIN X X VH OE# VIL VIH X VH VH X VIL or VIH VIL DQ DOUT High Z High Z High Z DIN High Z High Z/ DOUT Manufacturer’s ID (BFH) Device ID1 Address AIN AIN X X AIN X X AMS2 - A1 = VIL, A0 = VIL AMS2 - A1 = VIL, A0 = VIH T3.1 397 1. Device ID = C4H for SST37VF512, C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040 2. AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040 Note: X = VIL or VIH (or VH in case of OE# and A9) VH = 12V±5% Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (