SST39VF016-55-4I-B3I

8 Mbit / 16 Mbit (x8) Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 SST39LF/VF080 / 0163.0 & 2.7V 8Mb / 16Mb (x8) MPF memories Data Sheet FEATURES: • Organized as 1M x8 / 2M x8 • Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF080/016 – 2.7-3.6V for SST39VF080/016 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) – Standby Current: 4 µA (typical) – Auto Low Power Mode: 4 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Block-Erase Capability – Uniform 64 KByte blocks • Fast Read Access Time: – 55 ns for SST39LF080/016 – 70 and 90 ns for SST39VF080/016 • Latched Address and Data • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 15 seconds (typical) for SST39LF/VF080 30 seconds (typical) for SST39LF/VF016 • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 40-lead TSOP (10mm x 20mm) – 48-ball TFBGA (6mm x 8mm) PRODUCT DESCRIPTION The SST39LF/VF080 and SST39LF/VF016 devices are 1M x8 / 2M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF080/016 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF080/016 write (Program or Erase) with a 2.7-3.6V power supply. They conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF/ VF080 and SST39LF/VF016 devices provide a typical Byte-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF/VF080 and SST39LF/VF016 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 1 They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39LF/VF080 and SST39LF/VF016 are offered in 40lead TSOP and 48-ball TFBGA packaging. See Figures 1 and 2 for pinouts. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39LF/VF080 and SST39LF/VF016 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15 mA to typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high. are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39LF/VF080 and SST39LF/VF016 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte-command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte-command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Read The Read operation of the SST39LF/VF080 and SST39LF/VF016 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Chip-Erase Operation The SST39LF/VF080 and SST39LF/VF016 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Byte-Program Operation The SST39LF/VF080 and SST39LF/VF016 are programmed on a byte-by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads ©2001 Silicon Storage Technology, Inc. Write Operation Status Detection The SST39LF/VF080 and SST39LF/VF016 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. S71146-03-000 6/01 396 2 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39LF/VF080 and SST39LF/VF016 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF080 and SST39LF/VF016 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. Data# Polling (DQ7) When the SST39LF/VF080 and SST39LF/VF016 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart. Common Flash Memory Interface (CFI) The SST39LF/VF080 and SST39LF/VF016 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 8. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Data Protection The SST39LF/VF080 and SST39LF/VF016 provide both hardware and software features to protect nonvolatile data from inadvertent writes. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 3 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Product Identification The Product Identification mode identifies the device as the SST39LF080, SST39VF080, SST39LF016, and SST39VF016 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST39LF/VF080 SST39LF/VF016 0001H 0001H D8H D9H T1.2 396 Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart. Data BFH 0000H FUNCTIONAL BLOCK DIAGRAM X-Decoder SuperFlash Memory Memory Address Address Buffer & Latches Y-Decoder CE# OE# WE# DQ7 - DQ0 396 ILL B1.2 Control Logic I/O Buffers and Data Latches ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 4 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet SST39LF/VF160 SST39LF/VF080 A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 SST39LF/VF080 SST39LF/VF016 A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 Standard Pinout Top View Die Up 396 ILL F01.2 FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP TOP VIEW (balls facing down) TOP VIEW (balls facing down) SST39LF/VF080 SST39LF/VF016 NC VSS 6 5 4 3 2 1 A14 A13 A15 A9 A8 A11 NC NC A6 A2 A16 A17 NC 6 5 4 3 396 ILL F20.1 A14 A13 A15 A9 A8 A11 NC NC A6 A2 A16 A17 NC A20 VSS A12 A19 A10 DQ6 DQ7 NC DQ5 NC VDD DQ4 A12 A19 A10 DQ6 DQ7 NC DQ5 NC VDD DQ4 WE# NC NC A7 A3 NC A18 A4 WE# NC NC A7 A3 NC A18 A4 NC DQ2 DQ3 VDD NC A5 A1 DQ0 NC NC DQ1 NC DQ2 DQ3 VDD NC A5 A1 DQ0 NC NC DQ1 396 ILL F21.1 2 1 A0 CE# OE# VSS A0 CE# OE# VSS A B C D E F G H A B C D E F G H FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 5 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 2: PIN DESCRIPTION Symbol AMS1-A0 DQ7-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF080/016 2.7-3.6V for SST39VF080/016 CE# OE# WE# VDD VSS NC Chip Enable Output Enable Write Enable Power Supply Ground No Connection Unconnected pins. T2.3 396 1. AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016 TABLE 3: OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4 T3.4 396 CE# VIL VIL VIL VIH X X OE# VIL VIH VIH X VIL X WE# VIH VIL VIL X X VIH DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X 1. X can be VIL or VIH, but no other value. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 6 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase Software ID Software ID CFI Exit Entry4,5 Exit6/ CFI Query Entry4 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H T4.3 396 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data A0H 80H 80H 80H 90H 98H 4th Bus Write Cycle Addr1 WA2 5555H 5555H 5555H Data Data AAH AAH AAH 5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 6th Bus Write Cycle Addr1 SAX3 BAX 3 Data 30H 50H 10H 5555H Software ID Exit6/ CFI Exit 1. Address format A14-A0 (Hex), Addresses A15 - A19 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080. Addresses A15 - A20 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF016. 2. WA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX, for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016 4. The device does not remain in Software Product ID Mode if powered down. 5. With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0, SST39LF/VF080 Device ID = D8H, is read with A0 = 1 SST39LF/VF016 Device ID = D9H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080 AND SST39LF/VF016 Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 51H 52H 59H 01H 07H 00H 00H 00H 00H 00H 00H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T5.3 396 1. Refer to CFI publication 100 for more details. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 7 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 27H1 30H1 36H 00H 00H 04H 00H 04H 06H 01H 00H 01H 01H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no VPP pin) VPP max. (00H = no VPP pin) Typical time out for Byte-Program 2N µs (24 = 16 µs) Typical time out for min. size buffer program 2N µs (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) T6.1 396 FOR SST39VF320/640 1. 0030H for SST39LF080/016 and 0027H for SST39VF080/016 TABLE 7: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 14H 00H 00H 00H 00H 02H FFH 00H 10H 00H 0FH 00H 00H 01H FOR SST39LF/VF080 Data Device size = 2N Bytes (14H = 20; 220 = 1 MBytes) Flash Device Interface description; 0000H = x8-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 255 + 1 = 256 sectors (00FFH = 255) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 15 + 1 = 16 blocks (000FH = 15) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T7.0 396 ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 8 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 8: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 15H 00H 00H 00H 00H 02H FFH 01H 10H 00H 1FH 00H 00H 01H FOR SST39LF/VF016 Data Device size = 2N Bytes (15H = 21; 221 = 2 MBytes) Flash Device Interface description; 0000H = x8-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FFH = 511) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001FH = 31) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T8.2 396 ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 9 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (