SST39VF6401-70-4C-B1K

16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories Data Sheet FEATURES: • Organized as 1M x16: SST39VF1601/1602 2M x16: SST39VF3201/3202 4M x16: SST39VF6401/6402 • Single Voltage Read and Write Operations – 2.7-3.6V • Superior Reliability – Endurance: 100,000 Cycles (Typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical) • Hardware Block-Protection/WP# Input Pin – Top Block-Protection (top 32 KWord) for SST39VF1602/3202/6402 – Bottom Block-Protection (bottom 32 KWord) for SST39VF1601/3201/6401 • Sector-Erase Capability – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Chip-Erase Capability • Erase-Suspend/Erase-Resume Capabilities • Hardware Reset Pin (RST#) • Security-ID Feature – SST: 128 bits; User: 128 bits • Fast Read Access Time: – 70 ns – 90 ns • Latched Address and Data • Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bits – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (6mm x 8mm) for 16M and 32M – 48-ball TFBGA (8mm x 10mm) for 64M • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39VF160x/320x/640x devices are 1M x16, 2M x16, and 4M x16 respectively, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF160x/320x/640x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST39VF160x/320x/640x devices provide a typical WordProgram time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF160x/320x/640x devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 1 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet To meet high density, surface mount requirements, the SST39VF160x/320x/640x are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 1 and 2 for pin assignments. first. The Program operation, once initiated, will be completed within 10 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF160x/320x/640x also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF160x/320x/640x offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The BlockErase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a sixbyte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms and Figure 23 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector(Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Read The Read operation of the SST39VF160x/320x/640x is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. Word-Program Operation The SST39VF160x/320x/640x are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 2 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 20 for a flowchart. Chip-Erase Operation The SST39VF160x/320x/640x provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 9 for timing diagram, and Figure 23 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart. TABLE 1: WRITE OPERATION STATUS Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase-Suspended Sector/Block Read from Non- Erase-Suspended Sector/Block Program Write Operation Status Detection The SST39VF160x/320x/640x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle Data Data Data DQ7# Toggle N/A T1.0 1223 Data# Polling (DQ7) When the SST39VF160x/320x/640x are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately follow©2005 Silicon Storage Technology, Inc. Note: DQ7 and DQ2 require a valid address when reading status information. S71223-04-000 11/05 3 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet Data Protection The SST39VF160x/320x/640x provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 15). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39VF160x/320x/640x provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Hardware Block Protection The SST39VF1602/3202/6402 support top hardware block protection, which protects the top 32 KWord block of the device. The SST39VF1601/3201/6401 support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table 2. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. TABLE 2: BOOT BLOCK ADDRESS RANGES Product Bottom Boot Block SST39VF1601/3201/6401 Top Boot Block SST39VF1602 SST39VF3202 SST39VF6402 0F8000H-0FFFFFH 1F8000H-1FFFFFH 3F8000H-3FFFFFH T2.0 1223 Address Range 000000H-007FFFH Common Flash Memory Interface (CFI) The SST39VF160x/320x/640x also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 4 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet Product Identification The Product Identification mode identifies the devices as the SST39VF1601, SST39VF1602, SST39VF3201, SST39VF3202, SST39VF6401, SST39VF6402, and manufacturer as SST. This mode may be accessed software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart. TABLE 3: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST39VF1601 SST39VF1602 SST39VF3201 SST39VF3202 SST39VF6401 SST39VF6402 0001H 0001H 0001H 0001H 0001H 0001H 234BH 234AH 235BH 235AH 236BH 236AH T3.2 1223 Security ID The SST39VF160x/320x/640x devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details. Data BFH 0000H Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 13 for timing waveform, and Figures 21 and 22 for flowcharts. ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 5 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet FUNCTIONAL BLOCK DIAGRAM X-Decoder SuperFlash Memory Memory Address Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RESET# I/O Buffers and Data Latches Control Logic DQ15 - DQ0 1223 B1.0 SST39VF6401/6402 SST39VF3201/3202 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 WP# NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# NC WP# NC A18 A17 A7 A6 A5 A4 A3 A2 A1 SST39VF1601/1602 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RST# NC WP# NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1223 48-tsop P01.3 SST39VF160x/320x/640x A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Standard Pinout Top View Die Up FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 6 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet TOP VIEW (balls facing down) TOP VIEW (balls facing down) SST39VF1601/1602 SST39VF3201/3202 6 5 4 3 2 1 A13 A12 A14 A9 A8 A10 NC A15 A16 NC DQ15 VSS A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 NC DQ2 DQ10 DQ11 DQ3 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS 1223 48-tfbga B3K P02.0 6 5 4 3 2 1 A13 A12 A14 A9 A8 A10 NC A15 A16 NC DQ15 VSS A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 1223 48-tfbga B3K P02a.2 WE# RST# WE# RST# NC WP# A18 A7 A3 A17 A4 A6 A2 NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3 A7 A3 A17 A4 A6 A2 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS A B C D E F G H A B C D E F G H TOP VIEW (balls facing down) S ST39VF6401/6402 6 5 4 3 2 1 A13 A12 A14 A9 A8 A10 A15 A16 NC DQ15 VSS A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 WE# RST# A21 NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3 A7 A3 A17 A4 A6 A2 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS 1223 4-tfbga B1K P02b.2 ABCDEFGH FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 7 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet TABLE 4: PIN DESCRIPTION Symbol AMS1-A0 Pin Name Address Inputs Functions To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To protect the top/bottom boot block from Erase/Program operation when grounded. To reset and return the device to Read mode. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 2.7-3.6V Unconnected pins. T4.2 1223 DQ15-DQ0 Data Input/output WP# RST# CE# OE# WE# VDD VSS NC Write Protect Reset Chip Enable Output Enable Write Enable Power Supply Ground No Connection 1. AMS = Most significant address AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402 TABLE 5: OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 6 T5.0 1223 CE# VIL VIL VIL VIH X X OE# VIL VIH VIH X VIL X WE# VIH VIL VIL X X VIH DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT Address AIN AIN Sector or block address, XXH for Chip-Erase X X X 1. X can be VIL or VIH, but no other value. ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 8 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet TABLE 6: SOFTWARE COMMAND SEQUENCE Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H XXXXH XXXXH 5555H 5555H 5555H 5555H 5555H 5555H XXH Data2 AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH AAH F0H 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H Data2 A0H 80H 80H 80H 4th Bus Write Cycle Addr1 WA3 5555H 5555H 5555H Data2 Data AAH AAH AAH 5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 6th Bus Write Cycle Addr1 SAX4 BAX 4 Data2 30H 50H 10H 5555H 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 55H 55H 55H 55H 55H 55H 5555H 5555H 5555H 5555H 5555H 5555H 88H A5H 85H 90H 98H F0H WA6 XXH6 Data 0000H User Security ID Word-Program User Security ID Program Lock-Out Software ID Entry7,8 CFI Query Entry Software ID Exit9,10 /CFI Exit/Sec ID Exit Software ID Exit9,10 /CFI Exit/Sec ID Exit T6.6 1223 1. Address format A14-A0 (Hex). Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39VF1601/1602, Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF3201/3202, Addresses A15- A21 can be VIL or VIH, but no other value, for Command sequence for SST39VF6401/6402. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000010H to 000017H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39VF1601 Device ID = 234BH, is read with A0 = 1, SST39VF1602 Device ID = 234AH, is read with A0 = 1, SST39VF3201 Device ID = 235BH, is read with A0 = 1, SST39VF3202 Device ID = 235AH, is read with A0 = 1, SST39VF6401 Device ID = 236BH, is read with A0 = 1, SST39VF6402 Device ID = 236AH, is read with A0 = 1. AMS = Most significant address AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H. ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 9 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet TABLE 7: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF160X/320X/640X Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.1 1223 1. Refer to CFI publication 100 for more details. TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF160X/320X/640X Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0003H 0000H 0004H 0005H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no VPP pin) VPP max. (00H = no VPP pin) Typical time out for Word-Program 2N µs (23 = 8 µs) Typical time out for min. size buffer program 2N µs (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (25 = 32 ms) Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) T8.3 1223 TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF1601/1602 Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0015H 0001H 0000H 0000H 0000H 0002H 00FFH 0001H 0010H 0000H 001FH 0000H 0000H 0001H Data Device size = 2N Bytes (15H = 21; 221 = 2 MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FF = 511 z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001F = 31) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T9.0 1223 ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 10 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet TABLE 10: DEVICE GEOMETRY INFORMATION FOR SST39VF3201/3202 Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0016H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0010H 0000H 003FH 0000H 0000H 0001H Data Device size = 2N Bytes (16H = 22; 222 = 4 MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 (03FFH = 1023) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (003FH = 63) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T10.2 1223 TABLE 11: DEVICE GEOMETRY INFORMATION FOR SST39VF6401/6402 Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0017H 0001H 0000H 0000H 0000H 0002H 00FFH 0007H 0010H 0000H 007FH 0000H 0000H 0001H Data Device size = 2N Bytes (17H = 23; 223 = 8 MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 2047 + 1 = 2048 sectors (07FFH = 2047) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y =127 + 1 = 128 blocks (007FH = 127) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T11.2 1223 ©2005 Silicon Storage Technology, Inc. S71223-04-000 11/05 11 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (