SST65P542R-8-C-SG

Remote Controller MCU SST65P542R SST65P542RRemote Controller MCU Data Sheet FEATURES: • 8-bit MCU Core – Enhanced 6502 Microprocessor Megacell emulating the reduced 6805 instruction set • 4 MHz Typical Oscillator Clock Frequency • 8 MHz Maximum Oscillator Clock Frequency • Low Voltage Operation: 2.2-3.2V • 20 Re-configurable General Purpose I/O pins • SuperFlash Memory – 16 KByte of Flash Memory – 128 Byte sectors for SoftPartition – 100,000 endurance cycles (typical) – 100 years data retention – Fast Write: - Chip-Erase: 70 ms (typical) - Sector-Erase: 18 ms (typical) - Byte-Program: 60 µs (typical) – In-Application Programming (IAP) • External Host Programming Mode for Programmer Support – JEDEC Standard Command Sets • 352 Byte On-Chip SRAM • In-System Programming (ISP) Support through Firmware • IR Input Pin for Learning Mode • Carrier Modulator Transmitter – Supports Baseband, Pulse Length Modulator (PLM), and Frequency Shift Keying (FSK) • Core Timer / Counter – 14-stage multifunctional ripple counter – Includes timer overflow, POR, RTI, and CWT • External Reset and Low Power Reset Pins – One of these pins should be used to connect the external Power-on/Brown-out reset circuitry • Power Management – Hardware enable bits programmable by software for entering STOP and IDLE modes • Package Available – 28-lead SOIC • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST65P542R is a member of SST’s 8-bit applicationspecific microcontroller family targeted for infrared remote controller applications. The SST65P542R microcontroller provides high functionality to infrared remote controller products. The device offers flexibility to store different remote control configurations for controlling multiple appliances. The configurations are either programmed at the factory during the manufacturing process or downloaded through firmware. Using SST’s SuperFlash nonvolatile memory technology, the SST65P542R enhances the functionality and reduces the cost of conventional universal remote controller devices by integrating the multiple functions of a remote controller system in a single chip solution. The built-in LED I/O ports can directly drive LED indicators. The IR transmitter port drives signals to the infrared transmitter, which, in turn, remotely controls the appliances. The SoftPartition architecture allows seamless flash memory partitioning of the program code, protocol tables, and user data in the small granularity of 128 Byte sectors. The small sector size and fast Write capability of the device greatly decreases the time and power when altering the contents of the flash memory. The highly reliable, patented SuperFlash technology provides significant advantages over conventional flash memory technology. These advantages translate into significant cost savings and reliability benefits for customers. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SoftPartition is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Remote Controller MCU SST65P542R Data Sheet TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.0 I/O REGISTERS AND MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 SuperFlash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 PARALLEL INPUT/OUTPUT PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 In-Application Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 External Host Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 External Low Power Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Internal Power-on and Brown-out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 COP Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.0 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 CMT Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 Core Timer Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.0 OPERATION MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 Learning Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 2 Remote Controller MCU SST65P542R Data Sheet 9.0 PERIPHERALS AND OTHERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 Carrier Modulator Transmitter (CMT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3 Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.4 Crystal/Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5 External Clock Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.1 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3 DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 3 Remote Controller MCU SST65P542R Data Sheet LIST OF FIGURES FIGURE 2-1: Pin Assignments for 28-lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIGURE 3-1: Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 4-1: Port B Interrupt and Pull-Up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FIGURE 6-1: Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FIGURE 9-1: Using the Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 9-2: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 10-1: Stop Mode and Idle Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 11-1: External Host Programming Mode - Setup Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . 32 FIGURE 11-2: External Host Programming Mode - Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . 32 FIGURE 11-3: External Host Programming Mode - Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . 33 FIGURE 11-4: External Host Programming Mode - Chip-Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . 33 FIGURE 11-5: External Host Programming Mode Sector-Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . 34 FIGURE 11-6: External Host Programming Mode Byte-Program Timing Diagram . . . . . . . . . . . . . . . . . . . 34 FIGURE 11-7: AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 11-8: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 11-9: Byte-Program Command Sequence for External Host Programming Mode . . . . . . . . . . . . 36 FIGURE 11-10: Wait Options for External Host Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIGURE 11-11: Chip-/Sector-Erase Command Sequence for External Host Programming Mode . . . . . . . 38 LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TABLE 3-1: Register Descriptions and Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TABLE 3-5: Interrupt/Reset Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 5-1: SFFR Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TABLE 5-2: External Host Programming Mode Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TABLE 5-3: External Host Programming Mode Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 5-4: Software Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 8-1: Pin Assignment For Different Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 11-1: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TABLE 11-2: Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TABLE 11-3: DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 11-4: Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 11-5: External Host Programming-Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 13-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 4 Remote Controller MCU SST65P542R Data Sheet 1.0 FUNCTIONAL BLOCKS FUNCTIONAL BLOCK DIAGRAM MCU Core SuperFlash Memory 16K x8 Port A IRO Carrier Modulator Transmitter Port B Port C Interrupt Control IRQ# RAM 352K x8 Timer/Counter Interrupt Real-Time Counter Core Timer / Counter COP Watchdog Timer 1170 B1.8 ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 5 Remote Controller MCU SST65P542R Data Sheet 2.0 PIN ASSIGNMENTS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-lead SOIC Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1170 28-soic P01.5 OSC1 OSC2 VDD IRQ# RST# IRO VSS LPRST# PC3 PC2 PC1 PC0 PA7 PA6 FIGURE 2-1: PIN ASSIGNMENTS FOR 28-LEAD SOIC 2.1 Pin Descriptions TABLE Symbol PA[7:0] PB[7:0] PC[3:0] IRO LPRST# 2-1: PIN DESCRIPTIONS Type I/O1 I/O I/O O I Name and Functions Port A: The state of any pin in Port A is software programmable and every line is configured as an input during any reset. Port B: The state of any pin in Port B is software programmable and every line is configured as an input during any reset. Each I/O line contains a programmable interrupt/pull-up for keyscan. Port C: Every pin in Port C is a high-current pin and its state is software programmable. All lines are configured as inputs during any reset. IRO: Suitable for driving IR LED biasing logic, the IRO pin is the high-current source and sink output of the carrier modulator transmitter subsystem. Default state is low after any reset. Low-Power Reset: An active-low pin, LPRST# function sets MCU to low-power reset mode. Once the device is in low-power reset mode, it is held in reset with all processor clocks and crystal oscillator halted. An internal Schmitt trigger is included in the LPRST# pin to improve noise immunity. Reset: By setting the RST# pin low, the device is reset to a default state. An internal Schmitt trigger is included in the RST# pin to improve noise immunity. Oscillator 1,2: These 2 pins interface with external oscillator circuits. A crystal resonator, a ceramic resonator, or an external clock signal can be used. Interrupt Request: The IRQ# is negative edge-sensitive triggered. An internal Schmitt trigger is included in the IRQ# pin to improve noise immunity. Power Supply: Supply Voltage (2.2-3.2V) Ground: Circuit ground. (0V reference) T2-1.14 1170 RST# OSC1 OSC2 IRQ# VDD VSS I I O I PWR PWR 1. I = Input, O = Output ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 6 Remote Controller MCU SST65P542R Data Sheet 3.0 I/O REGISTERS AND MEMORY ORGANIZATION The SST65P542R has a total of 64 KByte of addressable memory space. A memory map is located in Figure 3-1. The on-chip memory consists of 32 Bytes of I/O registers, 352 Bytes of SRAM, 16 KByte of user flash memory and 128 Bytes of user vectors. 0180H Reserved 3FEFH CWT Reset 3FF0H 3FF1H Reserved 352 Bytes SRAM I/O Registers 0000H 001FH 0020H 017FH 0180H BFFFH C000H BFFFH User Memory 127 Sectors (128 Bytes per sector) Flash Memory (128 sectors) 16,256 Bytes FFF6H Core Timer Vector - (High Byte) FFF7H FFF8H FFF9H FFFAH FFFBH FFFCH FFFDH FFFEH FFFFH Core Timer Vector - (Low Byte) CMT Vector (High Byte) CMT Vector (Low Byte) IRQ/Port B Vector (High Byte) IRQ/Port B Vector (Low Byte) SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte) Flash Memory Read Protection FF80H FF81H FF7FH FF80H User Vector FFFFH Reserved FFF5H FFF6H Reset and Interrupt Vectors FFFFH 1170 F02.9 FIGURE 3-1: MEMORY MAP ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 7 Remote Controller MCU SST65P542R Data Sheet 3.1 I/O Registers The 32 Bytes of I/O registers occupy address locations from 0000H to 001FH that include general purpose I/O registers, the SuperFlash Function Register, and on-chip peripheral control registers. TABLE Symbol1 PORTA PORTB PORTC DDRA 3-1: REGISTER DESCRIPTIONS AND BIT DEFINITIONS (1 OF 2) Description Port A Data Register Port B Data Register Port C Data Register Reserved Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Reserved Core Timer Control and Status Register Core Timer Counter Register Port B Interrupt Control Register SuperFlash Function Register Port B Pull-up Control Register CWT Control Register Reserved Reserved Carrier Generator High Data Register 1 Carrier Generator Low Data Register 1 Carrier Generator High Data Register 2 Direct Address 0000H 0001H 0002H 0003H 0004H Bit Address, Bit Symbol Bit 7 PA7 PB7 DDRA7 Bit 6 PA6 PB6 DDRA6 Bit 5 PA5 PB5 DDRA5 Bit 4 PA4 PB4 DDRA4 Bit 3 PA3 PB3 PC3 DDRA3 Bit 2 PA2 PB2 PC2 DDRA2 Bit 1 PA1 PB1 PC1 DDRA1 Bit 0 PA0 PB0 PC0 DDRA0 Reset Value2,3 00H 00H 00H 00H DDRB 0005H DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 00H DDRC 0006H - - - - DDRC3 DDRC2 DDRC1 DDRC0 00H CTSCR 0007H 0008H CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0 03H CTCR 0009H CTD7 CTD6 CTD5 CTD4 CTD3 CTD2 CTD1 CTD0 00H PBIC 000AH INPRB7 INPRB6 INPRB5 INPRB4 INPRB3 INPRB2 INPRB1 INPRB0 00H SFFR 000BH PREN MEREN SEREN - PROG MERA SERA - 00H PBPUC 000CH - - - - - - PU1 PU0 03H CWTC CHR1 000DH 000EH 000FH 0010H IROLN CMTPOL PH5 PH4 PH3 PH2 PH1 CWT_EN PH0 00000001b 00UUUUUUb CLR1 0011H IROLP - PL5 PL4 PL3 PL2 PL1 PL0 00UUUUUUb CHR2 0012H - - SH5 SH4 SH3 SH2 SH1 SH0 00UUUUUUb ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 8 Remote Controller MCU SST65P542R Data Sheet TABLE Symbol1 CLR2 3-1: REGISTER DESCRIPTIONS AND BIT DEFINITIONS (CONTINUED) (2 OF 2) Description Carrier Generator Low Data Register 2 Modulator Control and Status Register Modulator Data Register 1 Modulator Data Register 2 Modulator Data Register 3 Power Saving Control Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved COP Watchdog Timer Reset Register Direct Address 0013H Bit Address, Bit Symbol Bit 7 Bit 6 Bit 5 SL5 Bit 4 SL4 Bit 3 SL3 Bit 2 SL2 Bit 1 SL1 Bit 0 SL0 Reset Value2,3 00UUUUUUb MCSR 0014H EOC DIV2 EIMSK EXSPC BASE MODE EOCIE MCGEN 00H MDR1 0015H MB11 MB10 MB9 MB8 SB11 SB10 SB9 SB8 UUUUUUUUb MDR2 0016H MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 UUUUUUUUb MDR3 0017H SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 UUUUUUUUb PSCR 0018H EN - - - - - STOP IDL 10000011b CWTC 0019H 001AH 001BH 001CH 001DH 001EH 001FH 3FF0H - - - - - - - CWT_CLR 01H T3-1.8 1170 1. “-” = reserved bits 2. “U” = unaffected by any reset 3. These registers can be reset by either external or internal reset. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 9 Remote Controller MCU SST65P542R Data Sheet PORT A Data Register (PORTA) Location 0000H 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 0 PA0 Reset Value 00H Symbol PA[7:0] Function Port A data register bit 0 to 7. These bits are for both reading and writing. Write the data to this register will output data to port A pins when it’s in output mode. If the pins are set to input mode, only the output data register is updated, port A pins are tri-stated. Reading the data from this register will read the state of port A pins when set in input mode. If the pins are set to output mode, it reads the output data register. See Table 3-2 for details. For a detailed explanation of each parallel I/O port, please refer to Section 4.0, “Parallel Input/Output Ports” on page 20. PORT B Data Register (PORTB) Location 0001H 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 Reset Value 00H Symbol PB[7:0] Function Port B data register bit 0 to 7. These bits are for both reading and writing. Writing data to this register will output data to port B pins when it’s in output mode. If the pins are set to input mode, only the output data register is updated, port B pins are tri-stated. Reading the data from this register will read the state of port B pins when set in input mode. If the pins are set to output mode, it reads the output data register. See Table 3-2 for details. PORT C Data Register (PORTC) Location 0003H 7 6 5 4 3 DDRC3 2 DDRC2 1 DDRC1 0 DDRC0 Reset Value 00H Symbol PC[3:0] Function Port C data register bit 0 to 3. These bits are for both reading and writing. Writing data to this register will output data to port C pins when it’s in output mode. If the pins are set to input mode, only output data register is updated, port C pins are tri-stated. Reading data from this register will read the state of port C pins when set in input mode. If the pins are set to output mode, it reads the output data register. See Table 3-2 for details. 3-2: I/O PIN FUNCTIONS AS GENERAL PURPOSE I/O DDRA, DDRB, DDRC 0 1 0 1 Mode Input Output Input Output I/O Pin Functions Data is written into the output data register. Data is written into the output data register and output to the I/O pins. The state of I/O is read The output data register is read T3-2.0 1170 TABLE Access Write Write Read Read ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 10 Remote Controller MCU SST65P542R Data Sheet PORT A Data Direction Register (DDRA) Location 0004H 7 DDRA7 6 DDRA6 5 DDRA5 4 DDRA4 3 DDRA3 2 DDRA2 1 DDRA1 0 DDRA0 Reset Value 00H Symbol DDRA[7:0] Function Port A data direction register bit 0 to 7. These bits are for both reading and writing. See Table 3-2 for details. 0: Port A is input 1: Port A is output PORT B Data Direction Register (DDRB) Location 0005H 7 DDRB7 6 DDRB6 5 DDRB5 4 DDRB4 3 DDRB3 2 DDRB2 1 DDRB1 0 DDRB0 Reset Value 00H Symbol DDRB[7:0] Function Port B data direction register bit 0 to 7. These bits are for both reading and writing. See Table 3-2 for details. 0: Port B is input 1: Port B is output PORT C Data Direction Register (DDRC) Location 0006H 7 6 5 4 3 PC3 2 PC2 1 PC1 0 PC0 Reset Value 00H Symbol DDRC[3:0] Function Port C data direction register bit 0 to 3. These bits are for both reading and writing. See Table 3-2 for details. 0: Port C is input 1: Port C is output PORT B Interrupt Control Register (PBIC) Location 000AH 7 INPRB7 6 INPRB6 5 INPRB5 4 INPRB4 3 INPRB3 2 INPRB2 1 INPRB1 0 INPRB0 Reset Value 00H Symbol INPRB[7:0] Function Port B interrupt control bits 0: Interrupt is enabled 1: Interrupt is disabled ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 11 Remote Controller MCU SST65P542R Data Sheet PORT B Pull-up Control Register (PBPUC) Location 000CH 7 6 5 4 3 2 1 PU1 0 PU0 Reset Value 03H Symbol PU1,PU0 Function Port B pull-up control bits. The following table shows pull-up strength. Defaults to strong pull-up when reset. 3-3: PULL-UP CONTROL BIT DESCRIPTION PU0 0 1 0 1 Pull-up No pull-up for Port B bit Weak pull-up for each Port B bit Weak pull-up for each Port B bit Strong pull-up for each Port B bit1 T3-3.1 1170 TABLE PU1 0 0 1 1 1. Default value after Power-on or Reset ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 12 Remote Controller MCU SST65P542R Data Sheet Core Timer Control Status Register (CTCSR) Location 0008H 7 CTOF 6 RTIF 5 TOFE 4 RTIE 3 TOFC 2 RTFC 1 RT1 0 RT0 Reset Value 03H Symbol CTOF Function Core timer overflow bit. CTOF is a real-only status bit, this bit is set when the 8-bit ripple counter rolls over from FFH to 00H. Writing to this bit has not effect. Reset clears CTOF. CTOF set to zero by writing a one to TOFC. Real-time Interrupt bit. RTIF is a read-only status bit. Writing has no effect on this bit. Reset clears RTIF. The real time interrupt circuit consists of a divider and a one-of-four selector. The input clock frequency that drives the RTI circuit is E/212 with three additional divider stages that allows a maximum interrupt period of 16 ms at the internal peripheral clock rate of 2.048 MHz. 0: Writing a one to RTFC clears the RTIF. 1: When the output of the chosen (one-of-four selector) stage goes active. RTIF TOFE Timer overflow enable bit. TOFE is statuses bit for both read and write. Reset clears this bit. 0: If the CTOF is not set or no timer overflow occurs. 1: If the CTOF is set and a CPU interrupt request is generated RTIE Real time interrupt enable bit. RTIE is a status bit for both read and write. Reset clears this bit. 0: If the RTIF is not set. 1: If the RTIF is set and a CPU interrupt request is generated. TOFC Timer overflow flag clear bit. This bit is for writing only. 0: Writing a zero has no effect on the CTOF bit. This bit always reads as zero. 1: When a one is written to this bit, CTOF is cleared. RTFC Real time interrupt flag clear bit. This bit is for writing only. 0: Writing a zero has no effect on the RTIF bit. This bit always reads as zero. 1: When a one is written to this bit, RTIF is cleared. RT[1:0] Real time interrupt rate select bit. These two bits select one of four taps from the interrupt logic. See Table 3-4. Reset sets these two bits, which selects the lowest periodic rate and gives the maximum. Care should be taken when altering RT0 and RT1 if the timeout period is imminent or uncertain. The CWT should be cleared before changing RTI taps. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. 3-4: RTI AND CWT RATES AT 4.096 MHZ OSCILLATOR, PRESCALER=1 RTI Rate RT1-RT0 212/E1 213/E 214/E 215/E 00 01 10 11 Minimum CWT Rates (215-212)/E (216-213)/E (217-214)/E (218-215)/E 14ms 28ms 56ms 112ms Maximum CWT Rates (215)/E (216)/E (217)/E (218)/E 16ms 32ms 64ms 128ms T3-4.2 1170 TABLE 2ms 4ms 8ms 16ms 1. E is the internal peripheral clock frequency and E = FOSC/2 ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 13 Remote Controller MCU SST65P542R Data Sheet Core Timer Counter Register (CTCR) Location 0009H 7 CTD7 6 CTD6 5 CTD5 4 CTD4 3 CTD3 2 CTD2 1 CTD1 0 CTD0 Reset Value 00H Symbol CTD[7:0] Function The core timer counter register bit 0 to bit 7. This is a read only status register in which contains the current value of the 8-bit ripple counter. This counter is clocked by the CPU clock (E/4) and can be used for various functions, including a software input capture. Extended time can be achieved by using the timer overflow function to increment a variable to simulate a 16-bit counter. SuperFlash Function Register (SFFR) Location 000BH 7 PREN 6 MEREN 5 SEREN 4 3 PROG 2 MERA 1 SERA 0 Reset Value 00H Symbol PREN Function Byte program enable bit. 0: Disable the byte program. 1: Enable the byte program. MEREN Mass (chip) program enable. 0: Disable the mass (chip) erase or program. 1: Enable the mass (chip) erase or program. SEREN Sector program enable. 0: Disable the sector erase or program. 1: Enable the sector erase or program. PROG Byte program control bit. 0: Not performs the byte program 1: Performs the byte program. MERA Mass (chip) program active bit. 0: Not performs the chip program 1: Performs the chip program. SERA Sector program active bit. 0: Not performs the sector program. 1: Performs the sector program. Therefore, when SFFR=22H, the MCU will perform the Sector-Erase, SFFR=44H, the MCU will perform the ChipErase, and SFFR=88H, the MCU will perform the Byte-Program. For a detailed explanation of MCU flash control, please refer to Section 5.1, “In-Application Programming” on page 21. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 14 Remote Controller MCU SST65P542R Data Sheet COP Watchdog Timer Control Register (CWTC) Location 000DH 7 6 5 4 3 2 1 0 CWT_EN Reset Value 01H Symbol CWT_EN Function COP watchdog timer enable bit. 0: COP watchdog timer is enabled. 1: COP watchdog timer is disabled. COP Watchdog Timer Reset Register (CWTR) Location 3FF0H 7 6 5 4 3 2 1 0 CWT_CLR Reset Value 01H Symbol CWT_CLR Function This bit is for writing only. For detail explanation of COP Watchdog Timer Reset, please refer to Section 6.4 0: Write zero to this bit will clear COP watchdog timer. 1: Write one to this bit has no effect. Read this bit will always returns one. Carrier Generator High Data Register1 (CHR1) Location 0010H 7 IROLN 6 CMTPOL 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 Reset Value 00UUUUUUb Symbol IROLN Function IRO latch control bit. Reading IROLN bit reads the state of the IRO latch. Writing IROLN updates the IRO latch with the data being written on the negative edge of the internal processor clock (FOSC/2). The IRO latch is clear out of reset. Writing to CHR1 to update IROLN will also update the primary carrier high data value. In addition, writing to CHR1 to update IROLN will update the CMT polarity bit. Bit 6 should contain the data of CMTPOL polarity bit. CMT output polarity bit. This bit controls the polarity of the CMT output (IRO). 0: the CMT output is active high. 1: the CMT output is active low. CMTPOL PH[5:0] Primary carrier high time data values. When selected, these bits contain the number of input clocks required to generate the carrier high time periods. When operating in timer mode, CHR1 and CLR1 are always selected. When operating in FSK mode, CHR1, CLR1 and CHR2, CLR2 are alternately selected under control of the modulator. The primary carrier high and low time values are undefined on the reset. These bits must be written to non-zero values that before the carrier generator is enabled to avoid spurious results. Bit 0 to Bit 7 of CHR1 can be used for both reading and writing. Note:“U” indicates that the bit is unaffected after reset. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 15 Remote Controller MCU SST65P542R Data Sheet Carrier Generator Low Data Register1 (CLR1) Location 0011H 7 IROLP 6 5 PL5 4 PL4 3 PL3 2 PL2 1 PL1 0 PL0 Reset Value 00UUUUUUb Symbol IROLP Function IRO latch control bit. Reading IROLP bit reads the state of the IRO latch. Writing IROLP updates the IRO latch with the data being written on the negative edge of the internal processor clock (FOSC/2). Writing to CLR1 to update IROLP will also update the primary carrier low data value. Care should be taken that bits 5-0 of the data to be written to CHR1 or CLR1. Primary carrier low time data values. The function of these bits is the same as PH[5:0]. PL[5:0] Carrier Generator High Data Register2 (CHR2) Location 0012H 7 6 5 SH5 4 SH4 3 SH3 2 SH2 1 SH1 0 SH0 Reset Value 00UUUUUUb Symbol SH[5:0] Function Secondary carrier high time data values. When selected, these bits contain the number of input clocks required to generate the carrier high time periods. When operating in time mode, CHR2 and CLR2 is never selected. When operating in FSK mode, CHR2, CLR2 and CHR1, CLR1 are alternately selected under control of the modulator. The secondary carrier high and low time values are undefined on the reset. These bits must be written to nonzero values before the carrier generator is enabled when operating in FSK mode. Carrier Generator Low Data Register2 (CLR2) Location 0013H 7 6 5 SL5 4 SL4 3 SL3 2 SL2 1 SL1 0 SL0 Reset Value 00UUUUUUb Symbol SL[5:0] Function Secondary carrier low time data values. The function of these bits is the same as SH[5:0]. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 16 Remote Controller MCU SST65P542R Data Sheet Modulator Control and Status Register (MCSR) Location 0014H 7 EOC 6 DIV2 5 EIMSK 4 EXSPC 3 BASE 2 MODE 1 EOCIE 0 MCGEN Reset Value 00H Symbol EOC Function End of modulation cycle status bit. This bit is read only. EOC is set when a match occurs between the contents of the space period register SREG and the down counter. At the end of cycle, the counter is initialized with the contents of the mark period buffer, MBUFF and SREG is loaded with the space period buffer SBUFF. This flag is cleared by reading the MCSR followed by an access of MDR2 or MDR3. EOC is cleared by reset. 0: current modulation cycle in progress. 1: end of modulator cycle has occurred. Divide by two scaler bit. The divide-by-two prescaler causes the CMT to be clocked at the bus rate, when the two times of bus rate is enabled and the FOSC is disabled. Since this bit is not double buffered, this bit should not be set during a transmission. 0: divide-by-two prescaler disabled. 1: divide-by-two prescaler enabled. External Interrupt Mask bit. This bit is used to mask IRQ and keyscan interrupts. This bit is cleared by reset. 0: IRQ and keyscan interrupts enabled. 1: IRQ and keyscan interrupts disabled. Extended Space Enable bit. For detailed description of extended space operation, please refer to 65P542R Programming User’s Manual. 0: Extended space disabled. 1: Extended space enabled Baseband Enable bit. This bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. When BASE is cleared, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. This bit is cleared by reset. This bit is not double buffered and should not be written during a transmission. 0: Baseband disabled. 1: Baseband enabled. Mode select bit. This bit is cleared by reset. This bit is not double buffered and should not be written during a transmission. 0: CMT operates in Time mode. 1: CMT operates in FSK mode. Interrupt enable bit. Interrupt request will be generated when EOC is set and EOCIE is set. Otherwise, interrupt will not be generated 0: interrupt disabled. 1: interrupt enabled. Modulator and carrier generator enable bit. Set this bit will initialize the carrier and modulator and will enable all clocks. Once enabled, the carrier generator and modulator will function continuously. 0: if this bit is zero, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled and the modulator output is forced low. To prevent spurious operation, the user should initialize all data and control registers before enabling the system. This bit is cleared by reset. All bits except Bit 0 can be used for both reading and writing. 1: Modulator and carrier generator enabled. DIV2 EIMSK EXSPC BASE MODE EOCIE MCGEN ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 17 Remote Controller MCU SST65P542R Data Sheet Modulator Data Register 1 (MDR1) Location 0015H 7 MB11 6 MB10 5 MB9 4 MB8 3 SB11 2 SB10 1 SB9 0 SB8 Reset Value UUUUUUUUb Symbol MB[11:8] SB[11:8] Function MBUFF high 4 bits. SBUFF high 4 bits. These bits can be used for both reading and writing. Modulator Data Register 2 (MDR2) Location 0016H 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 Reset Value UUUUUUUUb Symbol MB[7:0] Function MBUFF lower 8 bits. These bits can be used for both reading and writing. Modulator Data Register 3 (MDR3) Location 0016H 7 SB7 6 SB6 5 SB5 4 SB4 3 SB3 2 SB2 1 SB1 0 SB0 Reset Value UUUUUUUUb Symbol SB[7:0] Function SBUFF lower 8 bits. The bits can be used for reading and writing. Power Saving Control Register (PSCR) Location 0018H 7 EN 6 5 4 3 2 1 STOP 0 IDL Reset Value 10000011b Symbol EN Function This bit enable or disable MCU to stop and idle mode. This bit can be used for both reading and writing. 0: STOP and IDLE mode enable 1: STOP and IDLE mode disable. STOP Stop mode enable bit 0: write 0 to this bit will make the device entering the stop mode if EN=0 1: write 1 to this bit has no effect. Read returns one. IDL Idle mode enable bit 0: write 0 to this bit will make the device entering the idle mode if EN=0 1: write 1 to this bit has no effect. Read returns one. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 18 Remote Controller MCU SST65P542R Data Sheet 3.2 SRAM There are 352 Bytes of SRAM available. The SRAM addresses start from location 0020H to 017FH. The stack pointer can address 64 Bytes of stack beginning at address location 00FFH and ending at 00C0H. TABLE 3-5: INTERRUPT/RESET SECTOR User Vectors Flash Memory Read Protection Unused Core Timer Vector - (High Byte) Core Timer Vector - (Low Byte) CMT Vector (High Byte) CMT Vector (Low Byte) IRQ/Port B Vector (High Byte) IRQ/Port B Vector (Low Byte) SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte) T3-5.5 1170 Address Location FF80H FF81H-FFF5H FFF6H FFF7H FFF8H FFF9H FFFAH FFFBH FFFCH FFFDH FFFEH FFFFH 3.3 SuperFlash Memory The SST65P542R has 16 KByte of SuperFlash EEPROM memory. The memory is organized as 128 sectors of 128 Bytes each. The minimum erasable memory unit is one sector or 128 Bytes. The user programmable flash memory occupies the address space from C000H to FF7FH. The user vector area consists of 128 Bytes starting from address location FF80H to FFFFH. Address FF80H is for flash memory read protection. There are five predetermined user vectors from FFF6H through FFFFH dedicated to the reset and interrupts. Every vector consists of two bytes to be loaded into program counter for jumping to an interrupt service routine (ISR). See Table 3-5 for detailed descriptions of these vectors. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 19 Remote Controller MCU SST65P542R Data Sheet 4.0 PARALLEL INPUT/OUTPUT PORTS 4.1 Port A Port A consists of eight individual pins driven by one data register and one direction register to control the usage of these pins as either inputs or outputs. All Port A pins are set to Input mode during any Reset. Software must set the right direction register first before performing any Read or Write operation. Any Read operation to the port that was set as output will read back the data from an internal latch register instead of the I/O pins. For details, please refer to Section 3.1 Port A data register and Port A data direction register. 4.2 Port B Port B pins are similar to Port A pins except that each of the Port B pins has a programmable interrupt generation option which can be enabled for any Port B pins. Port B pins have optional programmable pull-ups. There is a choice between pull-up strengths which could be selected by PU0 or PU1. For details, please refer to Section 3.1, Port B Interrupt Control Register and Port B Pull-up Control Register. VDD WEAK0 PU0 WEAK1 PU1 INPRB7 DDRB7 PB7 From all other Port B Pins . . . Interrupt Logic 1170 F03.3 FIGURE 4-1: PORT B INTERRUPT AND PULL-UP OPTIONS 4.3 Port C Port C is a 4-bit bi-directional port (PC3-PC0). Every Port C pin has high current driving capability. Reset clears the Port C Data Register and the data direction register, thereby returning the ports to inputs. For details, please refer to Section 3.1 Port C data register and Port C data direction register. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 20 Remote Controller MCU SST65P542R Data Sheet 5.0 FLASH MEMORY PROGRAMMING 5.1 In-Application Programming SST65P542R allows “In-Application Programming” (IAP) to update the user code in the internal 16 Kbyte SuperFlash memory. All Write/Erase operations require setting the enable bit in the SuperFlash Function Register (SFFR) located at 000BH. The following sections describe the operations that the MCU performs to alter the contents of SuperFlash Memory. For detailed explanation of the SuperFlash Function Register, please refer to Section 3.1. 5.1.1 Chip-Erase The Chip-Erase operation requires MEREN and MERA bits to be set to logical “1”. After setting these bits, writing any data to any address location of the flash memory will trigger the Chip-Erase operation. The MCU is idle while SST65P542R is busy doing erases on all memory locations. 5.1.2 Sector-Erase The Sector-Erase operation requires SEREN and SERA bits to be set to logical “1”. After setting these bits, writing any data to the address within the sector to be erased will erase the data in the sector. The MCU is idle while SST65P542R is busy doing erase on the sector. 5.1.3 Byte-Program The Byte-Program operation requires PREN and PROG bits to be set to logical “1”. After setting these bits, and then writing the data to the target address to be programmed. The MCU is idle while SST65P542R is busy doing programming on the byte. Refer to the following summary for all different functions. . 5.2 External Host Programming Mode The external host programming mode is to provide programmer access to the 16KB embedded flash memory of the SST65P542R. To enter the external host programming mode, users must follow the setup sequences on the pins (See Figure 11-1): 1. RY/BY# (pin 12) and POROUT# (pin 13) are output pins. Do not drive. 2. Drive RST# (pin 24) low. 3. Drive LPRST# (pin 21) low. 4. Drive LPRST# (pin 21) high after TRST. 5. Drive PROG_RST (pin 9) low. 6. Drive 9 clocks on TCLKIN. On each clock's rising edge provide one bit of data on TDIN (pin 19) as shown in Figure 11-1. The data bits are “11010011”. 7. Wait for RY/BY# (pin 12) and POROUT# to go high. 8. Drive at least 24 clocks on TCLKIN. 9. If Read-protect byte is set, then RY/BY# will go low. Otherwise, RY/BY# will stay high. If RY/BY# is low, wait for RY/BY# (pin 12) to go high. Now the SST65P542R is in external host programming mode and is ready for embedded flash Read or Write operations. Now the SST65P542R is in the external host programming mode and is ready for embedded flash by the external host Read or Write. As soon as the RST# is released to ‘1’, chip exits external host programming mode and then enters user mode. 5.2.1 External Host Mode Read Operation As shown in Figure 11-2, the Read operation needs two address setup cycles and one data setup cycle. The low to high transition on SCLK latches the high order address A[13:8] from the pin AD[5:0] while MODE[1:0] inputs are set to 0H; the low to high transition on SCLK latches the low order address A[7:0] from the pin AD[7:0] while the MODE[1:0] inputs are set to 3H and setting the signal OE# to low; the low to high transition on SCLK latches the data D[7:0] on the pin AD[7:0] while the MODE[1:0] is set to 1H for reading. After reading the data, the external host should set the signal OE# to high. TABLE 5-1: SFFR COMMANDS Command Writes to SFFR Comment 44H 22H 88H Erase the whole flash memory Erase the sector addressed by CXXXH Program one data byte to address CXXXH. Write data to CXXXH before Byte-Program can be performed, a Chip-Erase or Sector-Erase must be issued to erase the target programming locations. T5-1.1 1170 Function Chip-Erase Sector-Erase Byte-Program ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 21 Remote Controller MCU SST65P542R Data Sheet 5.2.2 External Host Mode Write Operation As shown in Figure 11-3, the Write operation needs two address setup cycles and one data setup cycle. The low to high transition on SCLK latches the high order address A[13:8] from the pin AD[5:0] while the MODE[1:0] inputs are set to 0H; the low to high transition on SCLK latches the TABLE Pins 8-1 10,20 11 9 13 12 17 18 21 19 23 22 26 low order address A[7:0] from the pin AD[7:0] while MODE[1:0] inputs are set to 2H; the low to high transition on SCLK latches the data D[0:7] from the pin AD[7:0] while the MODE[1:0] is set to 1H for writing. However, the actual Write operation to embedded flash memory occurs on the rising edge of WE#. 5-2: EXTERNAL HOST PROGRAMMING MODE PIN DESCRIPTIONS Symbol AD[7:0] MODE[1:0] SLCK PROG_RST POROUT# RY/BY# WE# OE# LPRST# TDIN TCLKIN VSS VDD Type1 I/O1 I I I O O I I I I I PWR PWR Name and Functions Embedded flash memory address and data bus multiplex on AD[7:0] by selecting MODE[1:0] Address and data bus selection bits in the external host programming mode Clock for latch address and data after entering the external host programming mode Reset signal for the external host programming mode Embedded flash memory power-on reset output Embedded flash Ready/Busy output. High is ready Write Enable: embedded flash memory data write enable, low active Output Enable: embedded flash memory data out enable, low active Signal for entering the external host programming mode Data input for entering the external host programming mode This clock will latch TDIN for entering the external host programming mode Ground: Circuit ground (0V reference) Power Supply: Supply voltage (3.2V) T5-2.3 1170 1. I = Input; O = Output 5.2.3 External Host Mode Byte-Program Operation This device is programmed on a byte by byte basis. The Byte-Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load the byte address and the byte data. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE#. The end of the Byte-Program operation can be determined by using the RY/BY#. Any commands written during the Byte-Program operation will be ignored. See Table 5-4 for the software command sequence, Figure 11-5 for the flash Byte-Program timing diagram, and Figure 11-9 for the Byte-Program command sequence flowchart. 5.2.4 External Host Mode Chip-Erase Operation. The device provides a Chip-Erase operation, which allows the user to erase the entire memory array to the '1's state. This is useful when the device must be quickly erased entirely. The Chip-Erase operation is initiated by executing a six-byte Software Data Protection command sequence, the last byte Sequence is the address 1555H with the ChipErase command 10H. The Chip-Erase operation begins with of the sixth write enable's (WE#) rising edge. The end of the Chip-Erase can be determined by using the signal RY/BY#. Any commands written during the Chip-Erase ©2005 Silicon Storage Technology, Inc. operation will be ignored. See Table 5-4 for the software command sequence, Figure 11-4 for the flash Chip-Erase timing diagram, and Figure 11-11 for the Chip-Erase command sequence flowchart. 5.2.5 External Host Mode Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 128 Bytes. The SectorErase operation is initiated by executing a six-byte command sequence for Software Data Protection, the last byte sequence is the sector address SA with the Sector-Erase command 30H. The address lines A[13:7] will be used to determine the sector address. The internal Erase operation begins after the sixth write enable's (WE#) rising edge. The End-of-Erase can be determined by using the signal RY/ BY#. Any commands written during the Sector-Erase operation will be ignored. See Table 5-4 for the software command sequence, Figure 11-5 for the flash Sector-Erase timing diagram, and Figure 11-11 for the Sector-Erase command sequence flowchart. S71170-06-000 7/05 22 Remote Controller MCU SST65P542R Data Sheet 5.2.6 Operation Status Detection - Program Timer Method During the Program or Erase operation, the programmer can use the timer to decide the completion of the operation. When a Program or Erase operation is started, system setup a timer for TBP (for Byte-Program), TSCE (for ChipErase), and TSE (for Sector-Erase) time period. After this timer time-out, the operation is completed. See Figure 1110 for Program Timer flowchart. 5.2.7 Operation Status Detection - RY/BY# Method During the internal Program or Erase operation, the signal RY/BY# indicates the status of the operation. When the internal Program or Erase operation is in progress, the signal RY/BY# will be driven low. When the internal Program or Erase operation is completed, the signal RY/BY# will be driven high. The device is then ready for the next operation. See Figure 11-10 for the Program Timer flowchart. 5.2.8 Exiting The External Host Programming Mode To exit the external host programming mode, the external host must set the RST# pin to high, and the PROG_RST is reset to high. The device will exit the host programming and enter the user mode. The MCU starts execution codes out of the User Memory Space from the reset vector. TABLE 5.2.9 Flash Read Protection To protect the program code from piracy the flash memory location 3F80H (user memory address FF80H, flash memory is mapped to C000H through FFFFH, see Figure 3-1) is evaluated by the internal hardware to determine the read protect mode state. During this evaluation period, only the RY/BY# pin is valid and all other pins are blocked. If this byte is A3H (read protect is active), a Chip-Erase will be performed by internal hardware before the external host programming mode is activated. While the Chip-Erase could take TSCE (See Table 11-5) as maximum time, users may use RY/BY# pin to determine the completion of the Chip-Erase. If this byte is not A3H (not read protected), all of the flash memory are visible by using the external host programming. During the internal Program or Erase operation, the signal RY/ BY# indicates the status of the operation. When the internal Program or Erase operation is in progress, the RY/BY# will be driven low. When the internal Program or Erase operation is completed, the RY/BY# will be driven high. The device is then ready for the next operation. See Figure 11-10 for the Program Timer flowchart. Note: After writing A3H to the flash read protection register, the device needs to continue power-on prior to finishing the programming function. The programming function may include the Program-Verify function. 5-3: EXTERNAL HOST PROGRAMMING MODE PIN ASSIGNMENT MODE0=0 MODE1=0 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] Input A8 Input A9 Input A10 Input A11 Input A12 Input A13 MODE0=0 MODE1=1 Input A0 Input A1 Input A2 Input A3 Input A4 Input A5 Input A6 Input A7 MODE0=1 MODE1=0 Input D0 Input D1 Input D2 Input D3 Input D4 Input D5 Input D6 Input D7 MODE0=1 MODE1=1 Output D0 Output D1 Output D2 Output D3 Output D4 Output D5 Output D6 Output D7 T5-3.1 1170 TABLE 5-4: SOFTWARE COMMAND SEQUENCE 1st Bus Write Cycle Addr1 1555H 1555H 1555H Data AAH AAH AAH 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 3rd Bus Write Cycle Addr1 1555H 1555H 1555H Data 80H 80H A0H 4th Bus Write Cycle Addr1 1555H 1555H WA3 Data AAH AAH Data T5-4.3 1170 Command Sequence Sector-Erase Chip-Erase Byte-Program 5th Bus Write Cycle Addr1 2AAAH 2AAAH Data 55H 55H 6th Bus Write Cycle Addr1 SAX2 1555H Data 30H 10H 1. Address format A13-A0 (Hex) 2. SAX for Sector-Erase; uses A13-A7 address lines 3. WA = Program Byte address ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 23 Remote Controller MCU SST65P542R Data Sheet 6.0 RESET The 65P542R can be reset from five sources: two external inputs and three internal restart conditions. OSC Data Address COP Watchdog Reset Illegal Address Reset Address Reset Control Internal Reset RST# LPRST# 4064 Bus Clock Cycle Delay 1170 F16.2 FIGURE 6-1: RESET BLOCK DIAGRAM During power-up, the internal power-on reset is asserted before VDD reaches VPOR. During power-down, the internal brown-out reset is asserted after VDD drops below VBOR. (See Table 11-2) 6.1 External Reset A low-level input on the RST# pin causes the program counter to be set to the contents of location FFFEH and FFFFH (Reset Vector). The MCU is initialized to a known state. Stack pointer will be reset to FFH. Hardware Reset is the highest priority input to the chip. An internal Schmitt trigger is implemented on the RST# input to enhance the noise immunity. 6.4 COP Watchdog Timer Reset SST65P542R has a COP (Computer Operating Properly) watchdog timer for monitoring the proper operations of MCU. In normal operation, clearing the COP watchdog timer is executed by software within a preset period of time to avoid reaching time-out condition. To clear the COP watchdog timer, software write “0” to location 3FF0H. The COP Watchdog Reset is asserted and resets the MCU when the time-out condition occurs. The COP watchdog timer is disabled during any external reset. To enable CWT, write logical “0” to CWT control register (000DH). Refer to the SST65P542R Programming User’s Manual for more information. 6.2 External Low Power Reset The LPRST# is one of the two external sources of a reset. The signal LPRST# allows the MCU to go into low power reset mode. All clocks and oscillator to the processor are halted when the LPRST# is held low. After the LPRST# is de-asserted (driven high), a delay of 4064 bus clock cycles is automatically enabled to wait for stable crystal oscillation. This pin also implements an internal Schmitt trigger to enhance the noise immunity. 6.3 Internal Power-on and Brown-out Reset The internal power-on and brown-out reset signal will inhibit flash Erase or Program operations during the power-on or brown-out unstable period to prevent inadvertent Writes to flash memory. The reset signal only affects flash Erase and Program operations. It will not reset other circuits of the device. 6.5 Illegal Address Reset An illegal address reset is generated when the MCU attempts to fetch an instruction from I/O address space (0000H to 001FH). Those addresses are reserved for I/O registers only. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 24 Remote Controller MCU SST65P542R Data Sheet 7.0 INTERRUPTS SST65P542R accepts five sources of interrupts with highest to lowest priority: Software Interrupt, External Interrupts (IRQ# pin / Port B), CMT Interrupt, and Core Timer Interrupt. Whenever multiple interrupt requests are active at the same time, the higher priority one will be serviced first. All interrupts are maskable except Software Interrupt which is generated by executing SWI instruction. To mask interrupts, set the interrupt mask bit of Process Status Word (PSW). Before serving the interrupt, the MCU registers are pushed onto the stack in the sequence of PCL, PCH, IDX, ACC, PSW. The interrupt service routine should clear the source of interrupt before exiting. By executing RTI instruction, the stored MCU registers are popped from the stack and the program resumes from the interrupted location. The external interrupts, IRQ# pin and Port B interrupts are edge-sensitive and asserted on the falling edge of the pins. The Port B Interrupt Control Register enables or disables interrupts on each individual pin of port B. The External Interrupt Mask Bit (EIMSK) of Modulator Control and Status register can be used to mask all external interrupts so that lower priority interrupts such as timer interrupts can be served. The state of any external interrupt received during the masked period is preserved. When the EIMSK bit is clear, the pending interrupts activate the MCU interrupt processing again. The external interrupt causes MCU to load the contents of memory locations FFFAH and FFFBH into the Program Counter. 7.3 CMT Interrupt 7.1 Software Interrupt The SWI instruction causes MCU to load the contents of memory locations FFFCH and FFFDH into Program Counter regardless of the interrupt mask bit in PSW register. A CMT interrupt is generated when the end of cycle flag (EOC) and the end of cycle interrupt enable (EOCIE) bits are set in the modulator control and status register (MCSR). This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations FFF8H and FFF9H. 7.2 External Interrupts Upon completion of the current instruction, the MCU responds to the interrupt request that is latched internally. IRQ# must be asserted (low) for at least one TILIH (125 ns). Following the completion of the current instruction, the interrupt latch is tested. If both interrupt mask bit (I bit) in the PSW is clear and the interrupt request is pending, the interrupt service routine is entered. An external resistor to VDD is required by the IRQ# input for wired-AND operation. 7.4 Core Timer Interrupt The core timer is a 14-stage multifunctional ripple timer. User can select overflow or real-time interrupt by the setting of the Core Timer Control Status Register. Please see the timer section for more details. The timer interrupt causes MCU to load the contents of memory locations FFF6H and FFF7H into the Program Counter. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 25 Remote Controller MCU SST65P542R Data Sheet 8.0 OPERATION MODES The device can operate in two different modes. The Operation mode includes the User mode and the Learning mode. The pin definitions vary between different operation modes as described in Table 8-1. 8.2 Learning Mode To enter the learning mode, input the IR signal to the IRQ# pin, then use the BIL and BIH instruction set to record the input signal width. For detail information on learning mode, please refer to the application note Remote Controller Learning Algorithm using SST65P542R. 8.1 User Mode In the user mode, the embedded MCU fetches program codes from the user memory space. Please refer to the SST65P542R Programming User’s Manual for instruction sets and the internal MCU programming information. TABLE Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 8-1: PIN ASSIGNMENT FOR DIFFERENT OPERATION MODES Normal Interface Modes User Mode PB[0] PB[1] PB[2] PB[3] PB[4] PB[5] PB[6] PB[7] PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PC[0] PC[1] PC[2] PC[3] LPRST# VSS IRO RST# IRQ# VDD OSC2 OSC1 Learning Mode PB[0] PB[1] PB[2] PB[3] PB[4] PB[5] PB[6] PB[7] PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PC[0] PC[1] PC[2] PC[3] LPRST# VSS IRO RST# IRIN VDD OSC2 OSC1 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] PROG_RST MODE[1] SCLK RY/BY# POROUT# VIL VIL VIH WE# OE# TDIN MODE[0] LPRST# VSS TCLKIN VIL VIH VDD Do not use2 VIL T8-1.8 1170 External Host Programming Mode1 1. See Table 5-2 for pin description. 2. OSC2 is an output, not used during external host program mode. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 26 Remote Controller MCU SST65P542R Data Sheet 9.0 PERIPHERALS AND OTHERS 9.1 Core Timer Core Timer provides the following features: 1. Real Time Interrupt (RTI) 2. Timer Overflow 3. COP watchdog timer 4. Power-on reset (POR) Please refer to SST65P542R Programming User’s Manual for programming information. 9.4 Crystal/Ceramic Resonator A crystal/ceramic oscillator circuit is shown in Figure 9-1. A ceramic resonator instead of a crystal may be used to reduce costs. It is recommended that the resonator and capacitors be mounted as close to the pins as possible to minimize output distortion. Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. 9.2 Carrier Modulator Transmitter (CMT) SST65P542R integrates a carrier modulator transmitter for supporting various encoding methods. The purpose of this module is to reduce the loading of the MCU. Three major functions are performed by this block: carrier generation, modulation, and transmission. Please refer to SST65P542R Programming User’s Manual for programming information. OSC1 30 pF 4.0 MHz 30 pF OSC2 VSS 5 MΩ 1170 F05a.6 9.3 Clock Input Options Control connections for the 2-lead on-chip oscillator are the OSC1 and OSC2 pins. OSC1 is input and OSC2 is output. A crystal resonator, ceramic resonator, or external clock signal can drive the oscillator. FIGURE 9-1: USING THE CRYSTAL EXTERNAL CLOCK SIGNAL DON'T CONNECT OSC1 OSC2 VSS 1170 F05b.3 FIGURE 9-2: EXTERNAL CLOCK DRIVE 9.5 External Clock Drive If external clock source is provided, OSC1 is the clock input and OSC2 is don’t connect. Leave OSC2 open. ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 27 Remote Controller MCU SST65P542R Data Sheet 10.0 POWER SAVING MODES SST65P542R provides two power saving modes: Stop mode and Idle mode. These two modes can be entered through the setting of the Power Saving Control Register. Refer to Section 3.1 for power saving control register. device is recovered from STOP mode. There are three conditions that will recover the device from the STOP mode: external IRQ#/Port B interrupt (EIMSK=0), RST# or external reset LPRST#. The STOP bit will be set to 1 when the device has been brought out of STOP mode. The interrupt mask bit (I bit) will not be affected. 10.1 STOP Mode Writing a logic '0' to the STOP bit of the Power Saving Control Register enters the STOP mode. To achieve the lowest possible power consumption, the implementation uses STOP bit to gate off the internal clock. See Figure 10-1 for illustration of clock arrangement in the STOP mode. Since there is no clock input, the internal states are maintained and not changed including I/O registers and RAM memory except that the core timer counter bits are cleared. The external IRQ interrupt can brought the device out of the STOP mode, but all other interrupts are not served until the 10.2 IDLE Mode Writing a logic '0' to the IDLE bit of the Power Saving Control Register enters the IDLE mode. In the IDLE mode, the timer is still running. Any internal or external interrupt will recover the device from IDLE mode. If both STOP and IDLE bits are '0', then STOP mode takes effect. The IDLE bit will be set to 1 when the device has been brought out of the IDLE mode. The interrupt mask bit (I bit) will not be affected. CLK Clock Generator ÷2 STOP CPU Peripherals IDLE 1170 F04.2 FIGURE 10-1: STOP MODE AND IDLE MODE ©2005 Silicon Storage Technology, Inc. S71170-06-000 7/05 28 Remote Controller MCU SST65P542R Data Sheet 11.0 ELECTRICAL SPECIFICATION 11.1 Absolute Maximum Stress Ratings Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125 °C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 °C to + 150 °C DC Voltage on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (