21N65M5

STL21N65M5 N-channel 650 V, 0.175 Ω 17 A PowerFLAT™ (8x8) HV , ultra low gate charge MDmesh™ V Power MOSFET Features Type STL21N65M5 VDSS @ TJmax 710 V RDS(on) max < 0.190 Ω ID 17 A (1) 1. The value is rated according to Rthj-case ■ ■ ■ 100% avalanche tested Low input capacitance and gate charge Low gate input resistance Application Switching applications Description The device is a N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. Figure 1. Internal schematic diagram Table 1. Device summary Marking 21N65M5 Package PowerFLAT™ (8x8) HV Packaging Tape and reel Order code STL21N65M5 May 2011 Doc ID 17438 Rev 4 1/14 www.st.com 14 Contents STL21N65M5 Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 Test circuits .............................................. 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 Doc ID 17438 Rev 4 STL21N65M5 Electrical ratings 1 Electrical ratings Table 2. Symbol VDS VGS ID (1) Absolute maximum ratings Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Value 650 ± 25 17 11 68 2.7 1.7 10.8 3 125 5 400 15 - 55 to 150 150 Unit V V A A A A A A W W A mJ V/ns °C °C ID (1) IDM (1),(2) (3) (3) ID ID IDM(2),(3) Drain current (pulsed) PTOT (3) Total dissipation at TC = 25 °C (steady state) Total dissipation at TC = 25 °C (steady state) Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Peak diode recovery voltage slope Storage temperature Max. operating junction temperature PTOT(1) IAR EAS dv/dt (4) Tstg Tj 1. The value is rated according to Rthj-case. 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of inch², 2oz Cu. 4. ISD ≤ 17 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD = 400 V. Table 3. Symbol Rthj-case Thermal data Parameter Thermal resistance junction-case max Value 1 45 Unit °C/W °C/W Rthj-amb(1) Thermal resistance junction-amb max 1. When mounted on 1inch² FR-4 board, 2 oz Cu Doc ID 17438 Rev 4 3/14 Electrical characteristics STL21N65M5 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On /off states Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 Min. 650 1 100 100 3 4 0.175 5 0.190 Typ. Max. Unit V µA µA nA V Ω VDS = Max rating Zero gate voltage drain current (VGS = 0) VDS = Max rating, TC=125 °C Gate-body leakage current (VDS = 0) VGS = ± 25 V Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source on resistance VGS = 10 V, ID = 8.5 A Table 5. Symbol Ciss Coss Crss Co(tr)(1) Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Equivalent capacitance time related Equivalent capacitance energy related Intrinsic gate resistance Total gate charge Gate-source charge Gate-drain charge VDS = 0 to 520 V, VGS = 0 44 pF Test conditions Min. Typ. 1950 46 3 Max. Unit pF pF pF VDS = 100 V, f = 1 MHz, VGS = 0 - - - 133 - pF Co(er)(2) RG Qg Qgs Qgd f = 1 MHz open drain VDD = 520 V, ID = 8.5 A, VGS = 10 V (see Figure 16) - 2.5 44 12 17 - Ω nC nC nC - - 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/14 Doc ID 17438 Rev 4 STL21N65M5 Electrical characteristics Table 6. Symbol td(off) tr tc tf Switching times Parameter Turn-off delay time Rise time Cross time Fall time Test conditions VDD = 400 V, ID = 11 A, RG = 4.7 Ω, VGS = 10 V (see Figure 17), (see Figure 20) Min. Typ. 37 10 24 12 Max Unit ns ns ns ns - - Table 7. Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 17 A, VGS = 0 ISD = 17 A, di/dt = 100 A/µs VDD = 100 V (see Figure 17) ISD = 17 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 17) Test conditions Min. 294 4 28 340 5 29 Typ. Max. Unit 17 68 1.5 A A V ns µC A ns µC A - 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 17438 Rev 4 5/14 Electrical characteristics STL21N65M5 2.1 Figure 2. ID (A) Electrical characteristics (curves) Safe operating area AM07068v2 Figure 3. K δ=0.5 Thermal impedance Zth PowerFLAT 8x8 HV 0.2 Op Lim era ite tion d by in t m his ax ar RD ea 10 S( o n) is 10µs 100µs 1ms Tj=150°C Tc=25°C Single pulse 0.1 10 -1 0.05 0.02 0.01 Single pulse 1 10ms VDS(V) 10 -5 10 -2 0.1 0.1 1 10 100 10 -4 10 -3 10 -2 tp (s) Figure 4. ID (A) 35 30 25 20 15 10 Output characteristics AM05493v1 Figure 5. ID (A) 35 7V 30 25 20 15 10 6V 5 5V Transfer characteristics AM05494v1 VGS=10V VDS=15V 5 0 0 5 10 15 20 25 30 VDS(V) 0 0 2 4 6 8 10 VGS(V) Figure 6. VGS (V) 12 10 Gate charge vs gate-source voltage Figure 7. AM05496v1 Static drain-source on resistance AM05495v1 VDD=520V ID=8.5A VGS 500 400 RDS(on) (Ω) 0.18 0.16 0.14 0.12 0.10 0.08 0 VGS= 10 V 8 300 6 200 4 2 0 0 10 20 30 40 50 100 0 Qg(nC) 2 4 6 8 10 12 14 16 ID(A) 6/14 Doc ID 17438 Rev 4 STL21N65M5 Figure 8. Eoss (µJ) 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 VDS(V) 1 0.1 1 10 100 1000 Electrical characteristics Figure 9. C (pF) 10000 Ciss Output capacitance stored energy AM05498v1 Capacitance variations AM05497v1 Coss Crss 10 100 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature VGS(th) (norm) 1.10 ID =250 µA AM05500v1 Figure 11. Normalized on resistance vs temperature RDS(on) (norm) 2.1 ID= 8.5 A 1.9 VGS= 10 V 1.7 1.5 AM05501v1 1.00 0.90 1.3 1.1 0.80 0.9 0.7 0.70 -50 -25 0 25 50 75 100 125 TJ(°C) 0.5 -50 -25 0 25 50 75 100 125 TJ(°C) Figure 12. Source-drain diode forward characteristics VSD (V) 1.0 0.9 0.8 TJ=25°C 0.7 TJ=150°C 0.6 0.5 0.4 0 10 20 30 40 50 ISD(A) AM05502v1 Figure 13. Normalized BVDSS vs temperature BVDSS (norm) 1.07 ID= 1 mA 1.05 1.03 1.01 0.99 0.97 0.95 0.93 -50 -25 0 25 50 75 100 TJ(°C) AM05499v1 TJ=-50°C Doc ID 17438 Rev 4 7/14 Electrical characteristics Figure 14. Switching losses vs gate resistance (1) STL21N65M5 E (μJ) 160 140 120 100 80 60 40 20 0 0 AM05541v1 ID=11A VDD=400V VGS=10V Eon Eoff 10 20 30 40 RG(Ω) 1. Eon including reverse recovery of a SiC diode 8/14 Doc ID 17438 Rev 4 STL21N65M5 Test circuits 3 Test circuits Figure 16. Gate charge test circuit VDD 12V 2200 Figure 15. Switching times test circuit for resistive load 47kΩ 100nF 1kΩ RL VGS VD RG PW D.U.T. μF 3.3 μF VDD Vi=20V=VGMAX 2200 μF IG=CONST 2.7kΩ 47kΩ PW 1kΩ 100Ω D.U.T. VG AM01468v1 AM01469v1 Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test switching and diode recovery times circuit A D G S B 25 Ω D.U.T. A FAST DIODE B A L=100μH B D G 3.3 μF 1000 μF L VD 2200 μF 3.3 μF VDD VDD ID RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform V(BR)DSS VD Figure 20. Switching time waveform Concept waveform for Inductive Load Turn-off Id 90%Vds 90%Id Tdelay-off -off IDM Vgs 90%Vgs on ID Vgs(I(t)) )) VDD VDD Vds 10%Vds 10%Id Trise Tfall AM01472v1 Tcross -over AM05540v2 Doc ID 17438 Rev 4 9/14 Package mechanical data STL21N65M5 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10/14 Doc ID 17438 Rev 4 STL21N65M5 Package mechanical data Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. A A1 b c D E D2 E2 e L 0.40 7.05 4.15 0.95 0.80 Typ. 0.90 0.02 1.00 0.10 8.00 8.00 7.20 4.30 2.00 0.50 0.60 7.30 4.40 Max. 1.00 0.05 1.05 Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data e L b BOTTOM VIEW PIN#1 ID E2 D 0.40 D2 INDEX AREA E SIDE VIEW TOP VIEW A A1 SEATING PLANE 0.08 C AM05542v1 Doc ID 17438 Rev 4 11/14 Package mechanical data STL21N65M5 Figure 22. PowerFLAT™ 8x8 HV recommended footprint 7.30 2.00 1.05 0.60 AM05543v1 12/14 Doc ID 17438 Rev 4 4.40 STL21N65M5 Revision history 5 Revision history Table 9. Date 28-Apr-2010 14-Jun-2010 14-Mar-2011 18-May-2011 Document revision history Revision 1 2 3 4 First release. RDS(on) typical value has been corrected. Figure 2: Safe operating area, Figure 3: Thermal impedance and Figure 7: Static drain-source on resistance have been updated. RDS(on) limits in Table 4 have been updated. Changes Doc ID 17438 Rev 4 13/14 STL21N65M5 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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