4027

H CC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP . . . . . . . . SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ”HIGH” OR ”LOW” MEDIUM SPEED OPERATION - 16MHz (typ. clock toggle rate at 10V) STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TEN0 TATIVE STANDARD N . 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES”. EY (Plastic Package) F (Ceramic Frit Seal Package) M1 (Micro Package) C1 (Plastic Chip Carrier) ORDER CODES : HCC4027BF HCF4027BM1 HCF4027BEY HCF4027BC1 PIN CONNECTIONS DESCRIPTION The HCC4027B (extended temperature range) and HCF4027B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals, Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the HCC/HCF4013B dual D-type flip-flop. The HCC/HCF4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop ; changes in the flipflop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input. June 1989 1/12 HCC/HCF4027B FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DD* Vi II Pt ot Parameter Supply Voltage : HCC Types HC F Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range Operating Temperature : HCC Types H CF Types Storage Temperature Value – 0.5 to + 20 – 0.5 to + 18 – 0.5 to V DD + 0.5 ± 10 200 100 – 55 to + 125 – 40 to + 85 – 65 to + 150 Unit V V V mA mW mW °C °C °C Top Tstg Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage . RECOMMENDED OPERATING CONDITIONS Symbol V DD VI Top Parameter Supply Voltage : HCC Types HC F Types Input Voltage Operating Temperature : HCC Types H CF Types Value 3 to 18 3 to 15 0 to V DD – 55 to + 125 – 40 to + 85 Unit V V V °C °C 2/12 HCC/HCF4027B LOGIC DIAGRAM AND TRUTH TABLE ONE OF TWO IDENTICAL J-K FLIP-FLOPS TRUTH TABLE Present State Inputs J I X O X X X X X K X O X I X X X X S O O O O O I O I R O O O O O O I I Output Q O I O I X X X X –/ –/ – – – – – CL ∆ Q I I O O Next State Outputs Q O O I I ← No Change I O I O I I /– /– \– X X X LOGIC I = HIGH LEVEL LOGIC O = LOW LEVEL ∆ - LEVEL CHANGE X - DON’T CARE 3/12 HCC/HCF4027B STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) Test Conditions Symbol Parameter VI (V) 0/ 5 HCC 0/10 Types 0/15 0/20 0/ 5 HCF 0/10 Types 0/15 V OH Output High Voltage 0/ 5 0/10 0/15 V OL Output Low Voltage 5/0 10/0 15/0 V IH Input High Voltage 0.5/4.5 1/9 4.5/0.5 9/1 0/ 5 HCC 0/ 5 Types 0/10 0/15 0/ 5 0/ 5 HCF Types 0/10 0/15 I OL Output Sink Current 0/ 5 HCC 0/10 Types 0/15 0/ 5 HCF 0/10 Types 0/15 I IH , I IL Input Leakage Current HCC Types 0/18 HCF Types 0/15 Any Input 2.5 4.6 9.5 13.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5