74AC161TTR

74AC161 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 125MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 161 IMPROVED LATCH-UP IMMUNITY DIP PACKAGE TUBE DIP SOP TSSOP 74AC161B 74AC161M ) s t( T&R o r P c u d 74AC161MTR 74AC161TTR counting and parallel loading and sets all outputs on LOW state. A LOW signal on LOAD overrides counting and allows information on Parallel Data inputs to be loaded into the flip-flop on the next rising edge of CLOCK. With LOAD and CLEAR HIGH, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting. The CARRY OUTPUT is HIGH when TE is HIGH and counter is in state 15. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. e t le o s b O - u d o r P e TSSOP ORDER CODES DESCRIPTION The 74AC161 is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. It is a 4 bit binary counter with Asynchronous Clear. The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, (CLEAR), (LOAD), (PE) and (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides ) s ( ct SOP PIN CONNECTION AND IEC LOGIC SYMBOLS t e l o s b O July 2001 1/13 74AC161 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 2 CLEAR CLOCK 3, 4, 5, 6 7 10 9 14, 13, 12, 11 15 8 16 A, B, C, D PE TE LOAD QA toQD Master Reset Clock Input (LOW to HIGH Edge Trigger) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip-Flop Outputs CARRY OUT Terminal Count Output GND Ground (0V) Positive Supply Voltage VCC TRUTH TABLE INPUTS CLEAR LOAD PE TE CK X L L A B FUNCTION L d o r L X X X H L X X H H X L NO CHANGE NO COUNT H H L X NO CHANGE NO COUNT H H H H H X X X P e let so b O - ) s ( ct LOGIC DIAGRAM u d o r P e t e l o s b O C L D PRESET TO "0" PRESET DATA COUNT UP COUNT NO CHANGE NO COUNT X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD 2/13 uc OUTPUTS ) s t( 74AC161 TIMING CHART c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 3/13 74AC161 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 300 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage Unit uc 2 to 6 V od -55 to 125 °C 8 ns/V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature dt/dv r P e t le Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) 1) VIN from 30% to 70% of V CC ) s ( ct u d o r P e t e l o s b O 4/13 ) s t( o s b O - 74AC161 DC SPECIFICATIONS Test Condition Symbol VIH Parameter High Level Input Voltage Low Level Input Voltage VIL High Level Output Voltage VOH VOL Low Level Output Voltage II Input Leakage Current Quiescent Supply Current ICC IOLD IOHD Dynamic Output Current (note 1, 2) Value TA = 25°C VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 VO = 0.1 V or VCC-0.1V Min. Typ. 2.1 3.15 3.85 1.5 2.25 2.75 1.5 2.25 2.75 VO = 0.1 V or VCC-0.1V Max. -40 to 85°C -55 to 125°C Min. Min. Max. 2.1 3.15 3.85 0.9 1.35 1.65 0.9 1.35 1.65 IO=-50 µA 2.9 2.99 2.9 2.9 IO=-50 µA 4.4 4.49 4.4 4.4 5.49 5.5 IO=-50 µA 5.4 5.4 5.4 3.0 IO=-12 mA 2.56 2.46 2.4 4.5 IO=-24 mA 3.86 3.76 3.7 5.5 IO=-24 mA 4.86 4.76 4.7 IO=50 µA 0.002 0.1 IO=50 µA 0.001 0.1 5.5 IO=50 µA 0.001 0.1 3.0 IO=12 mA 4.5 IO=24 mA 5.5 IO=24 mA 5.5 VI = VCC or GND 5.5 VI = VCC or GND 5.5 V 0.9 1.35 1.65 4.5 3.0 Max. 2.1 3.15 3.85 3.0 4.5 Unit uc 0.1 V V ) s t( 0.1 od 0.1 0.1 0.44 0.5 0.44 0.5 0.36 0.44 0.5 ± 0.1 ±1 ±1 µA 8 80 160 µA VOLD = 1.65 V max 75 50 mA VOHD = 3.85 V min -75 -50 mA (t s) 0.36 e t le 0.36 b O - so 0.1 Pr 0.1 V 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω o r P e c u d t e l o s b O 5/13 74AC161 AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter TA = 25°C VCC (V) -55 to 125°C Min. Min. 3.3(*) 7.0 12.0 13.0 13.0 (**) 5.0 9.0 10.0 10.0 tPLH tPHL Propagation Delay 3.3(*) Time CLOCK to 5.0(**) CARRY OUT tPLH tPHL Propagation Delay 3.3(*) Time TE to CARRY 5.0(**) OUT tPHL Propagation Delay 3.3(*) Time CLEAR to Q 5.0(**) Propagation Delay 3.3(*) tPHL Time CLEAR to 5.0(**) CARRY OUT 8.5 14.0 15.0 15.0 6.0 10.0 11.0 11.0 5.5 9.5 11.0 11.0 3.5 6.5 7.5 7.5 6.5 12.0 13.0 13.0 5.5 9.0 10.0 10.0 7.0 12.0 13.0 5.5 9.5 10.0 3.3(*) 3.0 5.5 7.5 ) s t( 5.0(**) 2.5 4.5 3.3(*) 2.0 3.5 (**) 5.0 2.0 3.0 d o r 6.0 3.5 3.5 3.3(*) 4.0 13.5 16.0 16.0 5.0(**) 1.5 8.5 10.5 10.5 -1.0 -1.0 0.5 0.5 -0.5 0.5 1.0 1.0 3.0 11.5 14.0 14.0 2.0 7.5 8.5 8.5 -2.5 0 0 0 -2.0 0.5 1.0 1.0 3.3(*) 3.0 6.0 7.0 7.0 5.0(**) 2.0 4.5 5.0 5.0 3.3(*) -1.0 0 0 0 5.0(**) -0.5 0 0.5 0.5 3.3(*) -1.0 0 0.5 0.5 (**) -0.5 0.5 1.0 1.0 CLEAR Pulse Width LOW tW ts th ts th CLOCK Pulse Width HIGH or LOW Setup Time HIGH or LOW (INPUT to CLOCK) Hold Time HIGH or LOW (INPUT to CLOCK) Setup Time HIGH or LOW (CLEAR to CLOCK) Hold Time HIGH or LOW (CLEAR to CLOCK) Setup Time HIGH or LOW (PE or TE to CLOCK) Hold Time HIGH or LOW (PE or TE to CLOCK) Recovery Time (CLEAR to CLOCK) Maximum Clock Frequency 3.3(*) (**) 5.0 3.3(*) ) s ( ct 5.0(**) 3.3(*) th r P e t e l o tREM bs fMAX (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V 5.0(**) 5.0 6.0 4.0 P e let o s b O - u d o ts 6/13 5.0 Max. Unit Max. tWL Min. -40 to 85°C Typ. tPLH tPHL Propagation Delay Time CLOCK to Q O Value Max. ns ns ns ns 13.0 10.0 uc 3.3(*) 70 90 60 60 5.0(**) 110 125 95 95 7.5 ns ns 4.0 ns ns ns ns ns ns ns ns MHz 74AC161 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25°C VCC (V) CIN Input Capacitance 5.0 CPD Power Dissipation Capacitance (note1) 5.0 Min. fIN = 10MHz Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 4.5 pF 18 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit) TEST CIRCUIT c u d e t le CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) ) s ( ct ) s t( o r P o s b O - WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle) u d o r P e t e l o s b O 7/13 74AC161 WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle) c u d o r P WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle) e t le ) s ( ct u d o r P e t e l o s b O 8/13 o s b O - ) s t( 74AC161 WAVEFORM 4: PROPAGATION DELAYS COUNTABLE MODE (f=1MHz; 50% duty cycle) c u d e t le ) s t( o r P o s b O - WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o s b O 9/13 74AC161 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 I 5.1 L c u d e t le 3.3 Z 1.27 ) s ( ct o s b O - o r P ) s t( 0.280 0.201 0.130 0.050 u d o r P e t e l o s b O P001C 10/13 74AC161 SO-16 MECHANICAL DATA mm. DIM. MIN. TYP A inch MAX. MIN. TYP. a1 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 ) s t( 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 G 4.6 5.3 0.181 L 0.5 1.27 0.019 M e t le 0.62 S 8° (max.) ) s ( ct o r P c u d 0.157 0.208 0.050 0.024 o s b O - u d o r P e t e l o s b O PO13H 11/13 74AC161 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 E 6.2 6.4 6.6 0.244 0.252 E1 4.3 4.4 4.48 0.169 0.173 1 e c u d 0.65 BSC K 0° L 0.45 0.60 A1 ) s ( ct u d o b r P e t e l o e o r P 0.260 0.176 0.0256 BSC e t le 8° A2 A ) s t( 0.201 0° 0.75 o s b O - 0.018 K c 8° 0.024 0.030 L E D s b O E1 PIN 1 IDENTIFICATION 1 0080338D 12/13 74AC161 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 13/13