74AC16373
16-BIT D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS (NON INVERTED)
■
■
■
■
■
■
■
HIGH SPEED:
tPD = 5.0 ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 8µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
50Ω TRASMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC16373 CMOS 16 BIT D-TYPE LATCH
with 3 STATE OUTPUTS NON INVERTING
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74AC16373TTR
PIN CONNECTION
1/10
74AC16373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
IEC LOGIC SYMBOLS
PIN DESCRIPTION
PIN No
SYMBOL
1
1OE
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs
11, 12
13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs
19, 20, 22, 23
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48
1LE
Latch Enable Input
4, 10, 15, 21,
GND
Ground (0V)
28, 34, 39, 45
7, 18, 31, 42
VCC
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUT
OE
LE
D
Q
H
L
L
L
X
L
H
H
X
X
L
H
Z
NO CHANGE *
L
H
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
2/10
74AC16373
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
Value
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
V
IIK
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
ICC or IGND DC VCC or Ground Current
Storage Temperature
Tstg
TL
Lead Temperature (10 sec)
± 50
mA
± 400
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature
dt/dv
Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1)
Value
Unit
2 to 6
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
8
ns/V
1) VIN from 30% to 70% of VCC
3/10
74AC16373
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
IOZ
ICC
IOLD
IOHD
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
TA = 25 °C
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
Value
VO = 0.1 V or
VCC-0.1V
Min.
Typ.
2.1
3.15
3.85
1.5
2.25
2.75
1.5
2.25
2.75
VO = 0.1 V or
VCC-0.1V
Max.
-55 to 125°C
Min.
Min.
Max.
2.1
3.15
3.85
0.9
1.35
1.65
0.9
1.35
1.65
V
0.9
1.35
1.65
3.0
IO=-50 µA
2.9
2.99
2.9
2.9
IO=-50 µA
4.4
4.49
4.4
4.4
5.49
5.5
IO=-50 µA
5.4
5.4
5.4
3.0
IO=-12 mA
2.56
2.46
2.46
4.5
IO=-24 mA
3.86
3.76
3.76
5.5
IO=-24 mA
4.86
4.76
4.76
Unit
Max.
2.1
3.15
3.85
4.5
V
V
3.0
IO=50 µA
0.002
0.1
0.1
0.1
4.5
IO=50 µA
0.001
0.1
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
0.1
3.0
IO=12 mA
0.36
0.44
0.44
4.5
IO=24 mA
0.36
0.44
0.44
5.5
IO=24 mA
0.36
0.44
0.44
5.5
VI = VCC or GND
± 0.1
±1
±1
µA
5.5
VI = VIH or VIL
VO = VCC or GND
± 0.5
±5
±5
µA
5.5
VI = VCC or GND
8
80
80
µA
VOLD = 1.65 V max
75
75
mA
VOHD = 3.85 V min
-75
-75
mA
5.5
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
4/10
-40 to 85°C
V
74AC16373
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
LE to Q
tPLH tPHL Propagation Delay
Time
D to Q
tPZL tPZH Output Enable
Time
tPLZ tPHZ Output Disable
Time
tW
ts
th
LE Pulse Width
HIGH
Setup Time D to
LE, HIGH or LOW
Hold Time D to LE,
HIGH or LOW
Value
TA = 25 °C
VCC
(V)
Typ.
Max.
3.3(*)
8.0
10.0
15.6
15.6
(**)
6.0
8.0
11.9
11.9
3.3(*)
8.3
11.0
15.1
15.1
5.0(**)
6.0
9.1
10.1
10.1
3.3(*)
5.0
Min.
-40 to 85 °C -55 to 125°C
Min.
Max.
Min.
Max.
11.8
19.8
22.3
22.3
(**)
7.4
11.3
12.8
12.8
3.3(*)
7.1
9.5
10.2
10.2
5.0(**)
5.9
8.0
8.8
8.8
5.0
3.3(*)
4.0
4.0
4.0
(**)
5.0
5.0
5.0
3.3(*)
1.5
1.5
1.5
(**)
1.5
1.5
1.5
5.0
5.0
3.3(*)
3
3
3
5.0(**)
2.5
2.5
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
VCC
(V)
Value
TA = 25 °C
Min.
CIN
Input Capacitance
COUT
Output Capacitance
Power Dissipation
Capacitance (note
1)
CPD
Typ.
Max.
-40 to 85 °C -55 to 125°C
Min.
Max.
Min.
Unit
Max.
5.0
3.5
pF
5.0
15
pF
25
pF
5.0
fIN=10MHz
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
5/10
74AC16373
TEST CIRCUIT
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
2VCC
tPZH, tPHZ
GND
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74AC16373
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74AC16373
TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
1.2
A1
0.05
0.047
0.15
A2
MAX.
0.002
0.006
0.9
0.035
b
0.17
0.27
0.0067
0.011
c
0.09
0.20
0.0035
0.0079
D
12.4
12.6
0.488
0.496
E
8.1 BSC
E1
6.0
0.318 BSC
6.2
e
0.236
0.5 BSC
0.244
0.0197 BSC
K
0˚
8˚
0˚
8˚
L
0.50
0.75
0.020
0.030
A
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
7065588C
8/10
74AC16373
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
30.4
0.519
1.197
Ao
8.7
8.9
0.343
0.350
Bo
13.1
13.3
0.516
0.524
Ko
1.5
1.7
0.059
0.067
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
9/10
74AC16373
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
10/10
