74ACT161B

74ACT161 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER s s s s s s s s s HIGH SPEED: fMAX = 290MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: V CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 161 IMPROVED LATCH-UP IMMUNITY DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE 74ACT161B 74ACT161M T&R 74ACT161MTR 74ACT161TTR DESCRIPTION The 74ACT161 is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS tecnology. It is a 4 bit binary counter with Asynchronous Clear. The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, (CLEAR), (LOAD), (PE) and (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state. A LOW signal on LOAD overrides PIN CONNECTION AND IEC LOGIC SYMBOLS counting and allows information on Parallel Data inputs to be loaded into the flip-flop on the next rising edge of CLOCK. With LOAD and CLEAR HIGH, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting. The CARRY OUTPUT is HIGH when TE is HIGH and counter is in state 15. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. April 2001 1/13 74ACT161 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 3, 4, 5, 6 7 10 9 14, 13, 12, 11 15 8 16 SYMBOL CLEAR CLOCK A, B, C, D PE TE LOAD QA toQD NAME QND FUNCTION Master Reset Clock Input (LOW to HIGH Edge Trigger) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip-Flop Outputs CARRY OUT Terminal Count Output GND Ground (0V) VCC Positive Supply Voltage TRUTH TABLE INPUTS CLEAR L H H H H H LOAD X L H H H X PE X X X L H X TE X X L X H X CLOCK X L A L B L C L D RESET TO "0" PRESET DATA NO COUNT NO COUNT COUNT NO COUNT OUTPUTS FUNCTION NO CHANGE NO CHANGE COUNT UP NO CHANGE X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD LOGIC DIAGRAM 2/13 74ACT161 TIMING CHART 3/13 74ACT161 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 300 -65 to +150 300 Unit V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 4 .5 to 5.5V (note 1) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -55 to 125 6 Unit V V V °C ns/V 1) VIN from 0.8V to 2.0V 4/13 74ACT161 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II ICCT ICC IOLD IOHD Input Leakage Current Max ICC/Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 µA IO=-50 µA IO=-24 mA IO=-24 mA IO=50 µA IO=50 µA IO=24 mA IO=24 mA VI = VCC or GND VI = VCC - 2.1V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 0.6 8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 ± 0.1 TA = 25°C Min. 2.0 2.0 Typ. 1.5 1.5 1.5 1.5 4.49 5.49 Max. Value -40 to 85°C Min. 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1 1.5 80 75 -75 0.8 0.8 4.4 5.4 3.7 4.7 0.1 0.1 0.5 0.5 ±1 1.6 160 50 -50 µA mA µA mA mA V Max. -55 to 125°C Min. 2.0 2.0 0.8 0.8 V Max. V Unit VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω 5/13 74ACT161 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) TA = 25°C Min. 1.5 1.5 Typ. 5.5 6.0 Max. 9.5 11.0 Value -40 to 85°C Min. Max. 10.5 12.0 -55 to 125°C Min. Max. 10.5 12.0 ns ns Unit tPLH tPHL Propagation Delay Time CLOCK to Q tPLH tPHL Propagation Delay Time CLOCK to CARRY OUT tPLH tPHL Propagation Delay Time TE to CARRY OUT Propagation Delay tPHL TimeCLEAR to CARRY OUT CLEAR Pulse t WL Width LOW CLOCK Pulse tW Width (LOAD ) HIGH or LOW CLOCK Pulse tW Width (COUNT) HIGH or LOW Setup Time HIGH ts or LOW (INPUT to CLOCK) Hold Time HIGH or th LOW (INPUT to CLOCK) Setup Time HIGH ts or LOW (LOAD to CLOCK) Hold Time HIGH or th LOW (LOAD to CLOCK) Setup Time HIGH ts or LOW (PE or TE to CLOCK) Hold Time HIGH or th LOW (PE or TE to CLOCK) Recovery Time tREM (CLEAR to Q) fMAX Maximum Clock Frequency (*) Voltage range is 5.0V ± 0.5V 5.0(*) 1.5 4.5 8.5 10.0 10.0 ns 5.0(*) 1.5 6.0 2.5 2.0 10.0 3.0 3.0 11.0 7.5 3.5 11.0 7.5 3.5 ns ns ns 5.0(*) 5.0(*) 5.0(*) 2.0 3.0 3.5 3.5 ns 5.0(*) 1.5 9.5 11.5 11.5 ns 5.0(*) -0.5 0 1.0 1.0 ns 5.0 (*) 2.0 8.5 9.5 9.5 ns 5.0 (*) -2.0 -0.5 0 0 ns 5.0(*) 1.5 5.5 6.5 6.5 ns 5.0(*) -2.0 -0.5 100 290 0 0.5 90 0.5 1.0 85 0.5 1.0 ns ns MHz 5.0(*) 5.0(*) 6/13 74ACT161 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 5.0 fIN = 10MHz TA = 25°C Min. Typ. 4 35 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = R 1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω ) WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle) 7/13 74ACT161 WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle) 8/13 74ACT161 WAVEFORM 4: PROPAGATION DELAYS COUNTABLE MODE (f=1MHz; 50% duty cycle) WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle) 9/13 74ACT161 Plastic DIP-16 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. P001C 10/13 74ACT161 SO-16 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013H 11/13 74ACT161 TSSOP16 MECHANICAL DATA mm MIN. A A1 A2 b c D E E1 e K L 0 o DIM. inch MAX. 1.1 MIN. TYP. MAX. 0.433 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 8 o TYP. 0.05 0.85 0.19 0.09 4.9 6.25 4.3 0.10 0.9 0.15 0.95 0.30 0.20 0.004 0.354 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176 5 6.4 4.4 0.65 BSC 4 o 5.1 6.5 4.48 0 o 4o 0.024 8o 0.028 0.50 0.60 0.70 0.020 A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 12/13 74ACT161 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 13/13