74ACT161MTR

74ACT161 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 290MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: V CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 161 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT161 is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS tecnology. It is a 4 bit binary counter with Asynchronous Clear. The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, (CLEAR), (LOAD), (PE) and (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state. A LOW signal on LOAD overrides DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP 74ACT161B 74ACT161M T&R 74ACT161MTR 74ACT161TTR counting and allows information on Parallel Data inputs to be loaded into the flip-flop on the next rising edge of CLOCK. With LOAD and CLEAR HIGH, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting. The CARRY OUTPUT is HIGH when TE is HIGH and counter is in state 15. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/13 74ACT161 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME QND FUNCTION 1 2 CLEAR CLOCK 3, 4, 5, 6 7 10 9 14, 13, 12, 11 15 8 16 A, B, C, D PE TE LOAD QA toQD Master Reset Clock Input (LOW to HIGH Edge Trigger) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip-Flop Outputs CARRY OUT Terminal Count Output GND Ground (0V) VCC Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLEAR LOAD PE TE CLOCK L X X X X H L X X H H X L NO CHANGE NO COUNT H H L X NO CHANGE NO COUNT H H H H COUNT UP COUNT H X X X NO CHANGE NO COUNT L L L L RESET TO "0" A B C D PRESET DATA X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD LOGIC DIAGRAM 2/13 74ACT161 TIMING CHART 3/13 74ACT161 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V V VI DC Input Voltage -0.5 to VCC + 0.5 VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 300 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Unit 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 1) VIN from 0.8V to 2.0V 4/13 Value Supply Voltage 0 to VCC V -55 to 125 °C 6 ns/V 74ACT161 DC SPECIFICATIONS Test Condition Symbol Parameter VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage VOL II ICCT ICC IOLD IOHD Low Level Output Voltage Input Leakage Current Max ICC/Input Quiescent Supply Current Dynamic Output Current (note 1, 2) Value TA = 25°C VCC (V) Min. Typ. 2.0 2.0 1.5 1.5 1.5 1.5 Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 4.5 5.5 4.5 5.5 VO = 0.1 V or VCC-0.1V 4.5 IO=-50 µA 4.4 4.49 4.4 4.4 5.5 IO=-50 µA 5.4 5.49 5.4 5.4 4.5 IO=-24 mA 3.86 3.76 3.7 5.5 IO=-24 mA 4.86 4.76 4.5 IO=50 µA 0.001 0.1 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 0.1 4.5 IO=24 mA 0.36 0.44 0.5 5.5 IO=24 mA 0.36 0.44 0.5 5.5 VI = VCC or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC - 2.1V 1.5 1.6 mA 5.5 5.5 VO = 0.1 V or VCC-0.1V 2.0 2.0 0.8 0.8 0.6 2.0 2.0 0.8 0.8 V 0.8 0.8 V 4.7 V 80 160 µA VOLD = 1.65 V max 75 50 mA VOHD = 3.85 V min -75 -50 mA VI = VCC or GND 8 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω 5/13 74ACT161 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CLOCK to Q tPLH tPHL Propagation Delay Time CLOCK to CARRY OUT tPLH tPHL Propagation Delay Time TE to CARRY OUT Propagation Delay tPHL TimeCLEAR to CARRY OUT CLEAR Pulse t WL Width LOW CLOCK Pulse tW Width (LOAD) HIGH or LOW CLOCK Pulse tW Width (COUNT) HIGH or LOW Setup Time HIGH ts or LOW (INPUT to CLOCK) Hold Time HIGH or th LOW (INPUT to CLOCK) Setup Time HIGH ts or LOW (LOAD to CLOCK) Hold Time HIGH or th LOW (LOAD to CLOCK) Setup Time HIGH ts or LOW (PE or TE to CLOCK) Hold Time HIGH or th LOW (PE or TE to CLOCK) Recovery Time tREM (CLEAR to Q) fMAX Maximum Clock Frequency (*) Voltage range is 5.0V ± 0.5V 6/13 VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0(*) Value TA = 25°C -55 to 125°C Min. Min. Typ. Max. 1.5 5.5 9.5 10.5 10.5 ns 1.5 6.0 11.0 12.0 12.0 ns 1.5 4.5 8.5 10.0 10.0 ns 1.5 6.0 10.0 11.0 11.0 ns 2.5 3.0 7.5 7.5 ns 2.0 3.0 3.5 3.5 ns 2.0 3.0 3.5 3.5 ns 1.5 9.5 11.5 11.5 ns -0.5 0 1.0 1.0 ns 2.0 8.5 9.5 9.5 ns -2.0 -0.5 0 0 ns 1.5 5.5 6.5 6.5 ns -2.0 0 0.5 0.5 ns -0.5 0.5 1.0 1.0 ns 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0 (*) 5.0 (*) 5.0(*) 5.0(*) 5.0(*) 100 290 90 Max. Unit Min. 5.0(*) 5.0(*) -40 to 85°C 85 Max. MHz 74ACT161 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter TA = 25°C VCC (V) CIN Input Capacitance 5.0 CPD Power Dissipation Capacitance (note 1) 5.0 Value Min. fIN = 10MHz Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 4 pF 35 pF 1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = R 1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle) 7/13 74ACT161 WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle) 8/13 74ACT161 WAVEFORM 4: PROPAGATION DELAYS COUNTABLE MODE (f=1MHz; 50% duty cycle) WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle) 9/13 74ACT161 Plastic DIP-16 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.77 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 10/13 74ACT161 SO-16 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.004 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 9.8 10 0.385 E 5.8 6.2 0.228 e 1.27 e3 0.393 0.244 0.050 8.89 0.350 F 3.8 4.0 0.149 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.157 0.024 8 (max.) P013H 11/13 74ACT161 TSSOP16 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC o K 0 L 0.50 A o 0.0256 BSC o o 4 8 0 4o 8o 0.60 0.70 0.020 0.024 0.028 A2 A1 b e K c E1 PIN 1 IDENTIFICATION 1 L E D 12/13 TYP. 74ACT161 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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