74ACT163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
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HIGH SPEED:
fMAX = 250MHz (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 8µA(MAX.) at TA=25°C
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), V IL = 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
IMPROVED LATCH-UP IMMUNITY
DIP
PACKAGE
TUBE
DIP
SOP
TSSOP
74ACT163B
74ACT163M
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74ACT163MTR
74ACT163TTR
parallel loading and sets all outputs on LOW state
on the next rising edge of CLOCK . A LOW signal
on LOAD overrides counting and allows
information on Parallel Data inputs to be loaded
into the flip-flop on the next rising edge of CLOCK.
With LOAD and CLEAR HIGH, PE and TE permit
counting when both are HIGH. Conversely, a
LOW signal on either PE and TE inhibits counting.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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ORDER CODES
DESCRIPTION
The 74ACT163 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS tecnology. It is a
4 bit binary counter with Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
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PIN CONNECTION AND IEC LOGIC SYMBOLS
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74ACT163
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
2
CLEAR
CLOCK
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
16
A, B, C, D
PE
TE
LOAD
QA toQD
Master Reset
Clock Input (LOW to
HIGH Edge Trigger)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
Flip-Flop Outputs
CARRY OUT Terminal Count Output
GND
Ground (0V)
Positive Supply Voltage
VCC
TRUTH TABLE
INPUTS
OUTPUTS
CLEAR
LOAD
PE
TE
L
X
X
X
L
L
L
H
L
X
X
A
B
C
H
H
X
L
NO CHANGE
H
H
L
X
NO CHANGE
H
H
H
H
H
X
X
X
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RESET TO "0"
PRESET DATA
NO COUNT
NO COUNT
COUNT UP
COUNT
NO CHANGE
NO COUNT
X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
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FUNCTION
74ACT163
TIMING CHART
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74ACT163
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Supply Voltage
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 50
mA
± 300
mA
-65 to +150
°C
300
°C
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Value
Supply Voltage
4.5 to 5.5
VI
Input Voltage
0 to VCC
VO
Output Voltage
Top
Operating Temperature
P
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let
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
dt/dv
1) VIN from 0.8V to 2.0V
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0 to VCC
-55 to 125
5
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V
V
V
°C
ns/V
74ACT163
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
Min.
Typ.
2.0
2.0
1.5
1.5
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
VIH
High Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VIL
Low Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VOH
High Level Output
Voltage
4.5
IO=-50 µA
4.4
4.49
4.4
4.4
5.5
IO=-50 µA
5.4
5.49
5.4
5.4
4.5
IO=-24 mA
3.86
3.76
3.7
5.5
IO=-24 mA
4.86
4.76
4.7
4.5
IO=50 µA
0.001
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
4.5
IO=24 mA
0.36
0.44
5.5
IO=24 mA
0.36
0.44
5.5
VI = VCC or GND
± 0.1
5.5
VI = VCC - 2.1V
od
VI = VCC or GND
VOL
Low Level Output
Voltage
II
ICCT
Input Leakage Current
Max ICC/Input
ICC
Quiescent Supply
Current
5.5
IOLD
Dynamic Output
Current (note 1, 2)
5.5
IOHD
2.0
2.0
1.5
1.5
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VOLD = 1.65 V max
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VOHD = 3.85 V min
8
Max.
2.0
2.0
0.8
0.8
0.6
Unit
0.8
0.8
±1
Pr
V
0.8
0.8
V
0.1
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0.1
V
0.5
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0.5
±1
µA
1.5
1.6
mA
80
160
µA
75
50
mA
-75
-50
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
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74ACT163
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
TA = 25°C
VCC
(V)
tPLH tPHL Propagation Delay
Time CLOCK to Q
tPLH tPHL Propagation Delay
Time CLOCK to
CARRY OUT
tPLH tPHL Propagation Delay
Time TE to CARRY
OUT
tW
CLOCK Pulse
Width, (Count)
HIGH or LOw
tW
CLOCK Pulse
Width, (Load) HIGH
or LOw
Setup Time HIGH
ts
or LOW (INPUT to
CLOCK)
th
Hold Time HIGH or
LOW (INPUT to
CLOCK)
Setup Time HIGH
ts
or LOW (CLEAR to
CLOCK)
th
Hold Time HIGH or
LOW (CLEAR to
CLOCK)
ts
Setup Time HIGH
or LOW (LOAD to
CLOCK)
th
Hold Time HIGH or
LOW (LOAD to
CLOCK)
ts
Setup Time HIGH
or LOW (PE or TE
to CLOCK)
Hold Time HIGH or
th
LOW (PE or TE to
CLOCK)
fMAX
Maximum Clock
Frequency
4.5
Value
(*)
4.5(*)
4.5(*)
1.5
5.0
10.0
11.0
11.0
ns
1.5
5.5
11.0
13.0
13.0
ns
1.5
3.5
9.0
10.5
10.5
ns
2.0
3.5
3.5
3.5
ns
2.0
3.5
3.5
2.0
4.0
5.0
-0.7
0.5
1.5
4.5(*)
4.5(*)
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(*) Voltage range is 5.0V ± 0.5V
6/13
4.5(*)
4.5(*)
120
Max.
Max.
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3.5
ns
5.0
ns
1.0
1.0
ns
3.0
4.0
4.0
ns
-0.5
0.5
1.0
1.0
ns
3.0
6.0
8.0
8.0
ns
-1.5
0
0.5
0.5
ns
3.0
5.5
6.5
6.5
ns
-1.5
0
0.5
0.5
ns
250
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4.5(*)
Min.
Max.
4.5(*)
4.5(*)
Min.
Unit
Typ.
4.5(*)
4.5(*)
-55 to 125°C
Min.
4.5(*)
4.5(*)
-40 to 85°C
105
105
MHz
74ACT163
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
CIN
Input Capacitance
5.0
CPD
Power Dissipation
Capacitance (note
1)
5.0
Min.
fIN = 10MHz
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
4
pF
35
pF
1) CPD is defined as the value of the IC’s internal equivqlent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
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CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
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WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
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74ACT163
WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle)
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WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle)
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74ACT163
WAVEFORM 4: PROPAGATION DELAYS COUNTABLE MODE (f=1MHz; 50% duty cycle)
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WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle)
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74ACT163
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
I
5.1
L
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3.3
Z
1.27
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0.280
0.201
0.130
0.050
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P001C
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74ACT163
SO-16 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
a1
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
E
5.8
6.2
0.228
0.393
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
G
4.6
5.3
0.181
L
0.5
1.27
0.019
M
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0.62
S
8 (max.)
)
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0.244
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0.157
0.208
0.050
0.024
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P013H
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74ACT163
TSSOP16 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
A
MIN.
TYP.
MAX.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
E
6.25
6.4
6.5
0.246
0.252
E1
4.3
4.4
4.48
0.169
0.173
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0.65 BSC
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K
0
L
0.50
A
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4
8
0.60
0.70
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1
uc
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0.256
0.176
0
4o
8o
0.020
0.024
0.028
K
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D
E1
PIN 1 IDENTIFICATION
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0.201
0.0256 BSC
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A2
A1
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MAX.
74ACT163
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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