74ACT273TTR

74ACT273 OCTAL D-TYPE FLIP FLOP WITH CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY DIP TSSOP ORDER CODES DESCRIPTION The 74ACT273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transfered to the Q output on the positive-going edge of the clock pulse. ) s ( ct SOP PACKAGE TUBE DIP SOP TSSOP 74ACT273B 74ACT273M ) s t( T&R o r P c u d 74ACT273MTR 74ACT273TTR When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. e t le o s b O - u d o r P e PIN CONNECTION AND IEC LOGIC SYMBOLS t e l o s b O April 2001 1/11 74ACT273 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 CLEAR 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 Q0 to Q7 Asyncronous Master Reset (Active LOW) Flip-Flop Outputs D0 to D7 Data Inputs CLOCK 10 20 GND VCC Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT ) s t( FUNCTION CLEAR D CLOCK Q X L L X H L L H H H H X X : Don’t Care LOGIC DIAGRAM ) s ( ct o s b O - u d o r P e t e l o s b O This logic diagram has not be used to estimate propagation delays 2/11 CLEAR d o r P e let Qn uc NO CHANGE 74ACT273 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 50 mA ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Unit uc Supply Voltage 4.5 to 5.5 VI Input Voltage 0 to VCC VO Output Voltage Top Operating Temperature dt/dv 1) VIN from 0.8V to 2.0V ) s ( ct d o r P e let Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) ) s t( V V 0 to VCC V -55 to 125 °C 8 ns/V o s b O - u d o r P e t e l o s b O 3/11 74ACT273 DC SPECIFICATIONS Test Condition Symbol Parameter Value TA = 25°C VCC (V) Min. Typ. 2.0 2.0 1.5 1.5 Max. -40 to 85°C -55 to 125°C Min. Min. Max. VIH High Level Input Voltage 4.5 5.5 VO = 0.1 V or VCC-0.1V VIL Low Level Input Voltage 4.5 5.5 VO = 0.1 V or VCC-0.1V VOH High Level Output Voltage 4.5 IO=-50 µA 4.4 4.49 4.4 4.4 5.5 IO=-50 µA 5.4 5.49 5.4 5.4 4.5 IO=-24 mA 3.86 3.76 3.7 4.86 VOL Low Level Output Voltage II ICCT Input Leakage Current Max ICC/Input 1.5 1.5 Max. 0.8 0.8 2.0 2.0 0.8 0.8 V 0.8 0.8 V 5.5 IO=-24 mA 4.5 IO=50 µA 0.001 0.1 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 0.1 4.5 IO=24 mA 0.36 0.44 5.5 IO=24 mA 0.36 0.44 5.5 VI = VCC or GND ± 0.1 ±1 5.5 VI = VCC - 2.1V ICC Quiescent Supply Current 5.5 VI = VCC or GND IOLD Dynamic Output Current (note 1, 2) 5.5 IOHD 2.0 2.0 4.76 4.7 1.5 P e let VOLD = 1.65 V max VOHD = 3.85 V min o s b O - V ) s t( 0.5 c u d ro 0.6 4 Unit 40 0.5 ±1 µA 1.6 mA 80 µA 75 50 mA -75 -50 mA 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (s) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CLOCK to Y tPHL Propagation Delay Time CLEAR to Y tWL CLEAR Pulse Width tW CLOCK Pulse Width ts Setup Time D to CLOCK, HIGH or LOW th Hold Time D to CLOCK, HIGH or LOW Recovery Time tREM CLEAR to CLOCK fMAX Maximum CLOCK Frequency o r P e t e l o bs O (*) Voltage range is 5.0V ± 0.5V 4/11 VCC (V) du ct Value TA = 25°C -40 to 85°C -55 to 125°C Unit Min. Typ. Max. Min. Max. Min. Max. 5.0(*) 1.5 4.0 8.5 1.5 9.0 1.5 9.0 ns 5.0(*) 1.5 4.5 9.0 1.5 9.5 1.5 9.5 ns 5.0(*) 2.3 4.0 4.0 4.0 ns 5.0(*) 1.8 4.0 4.0 4.0 ns 1.0 3.5 3.5 3.5 ns -0.5 1.5 1.5 1.5 ns 0.5 3.0 3.0 3.0 ns 5.0(*) 5.0(*) 5.0(*) 5.0(*) 125 190 110 110 MHz 74ACT273 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25°C VCC (V) CIN Input Capacitance 5.0 CPD Power Dissipation Capacitance (note 1) 5.0 Min. fIN = 10MHz Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 4 pF 32 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit) TEST CIRCUIT c u d e t le ) s ( ct CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) ) s t( o r P o s b O - u d o r P e t e l o s b O 5/11 74ACT273 WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) c u d e t le o s b O - WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o s b O 6/11 o r P ) s t( 74ACT273 WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle) c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 7/11 74ACT273 Plastic DIP-20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 I 3.93 L c u d e t le 3.3 Z 1.34 ) s ( ct o s b O - o r P ) s t( 0.280 0.155 0.130 0.053 u d o r P e t e l o s b O P001J 8/11 74ACT273 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A inch MAX. MIN. TYP. a1 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 E 10.00 10.65 0.393 0.419 c u d e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 L 0.50 1.27 0.19 M e t le 0.75 S 8 (max.) ) s ( ct ) s t( 0.512 o r P 0.299 0.050 0.029 o s b O - u d o r P e t e l o s b O P013L 9/11 74ACT273 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 E 6.25 6.4 6.5 0.246 0.252 E1 4.3 4.4 4.48 0.169 0.173 e r P e t le 0.65 BSC o K 0 L 0.50 A o r P e o 4 8 0.60 0.70 ) s ( ct du b e o s b O - o s b O 1 od 0.256 0.176 4o 8o 0.020 0.024 0.028 K L E c E1 PIN 1 IDENTIFICATION uc 0 D t e l o ) s t( 0.260 0.0256 BSC o A2 A1 10/11 MIN. 74ACT273 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 11/11