74ACT299

® 74ACT299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR PRELIMINARY DATA s s s s s s s s s HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 299 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT299B 74ACT299M These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1) as shown in the Truth Table. When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the high-impedance state ; however sequential operation or clearing of the register is not affected. Clear function is synchronous to clock. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The ACT299 is an high-speed CMOS 8-BIT PIPO SHIFT REGISTERS (3-STATE) fabricated with sub-micron silicon gate and double-layer metal 2 wiring C MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1999 1/13 74ACT299 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 11 12 18 10 20 SYMBOL S0, S1 G1, G2 A/QA to H/QH QA’ to QH’ CLEAR SR CLOCK SL GND VCC NAME AND F UNCTION Mode Select Inputs 3 State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asynchronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) Serial Data Shift Left Input Ground (0V) Positive Supply Voltage TRUTH TABLE MO DE CLEAR INPUTS F UNCTIO N OUTPUT SELECTED CONTRO L S1 S0 G1* G2* H L X L L L H H H H X L L H H L L H X L L L L L L L X X L L L L L L L X CLO CK INPUTS/OUTPUTS SERIAL A/Q A H/Q H SL X X X X X X X X X X H L X SR X X X X H L X X X Z L L QA0 H L QBn QBn a Z L L QH0 QGn QGn H L h L L L QA0 H L QBn QBn a L L L QH0 QGn QGn H L h O UT PUT S QA’ QH’ Z CLEAR HOLD SHIFT RIGHT SHIFT LEFT LOAD L L L H H H H H H * When one or both output controls are high, the eight, input/output terminals arethe high impedanc e state: howewer sequential operation or clearing of the register is not affected. Z : HIGH IMPEDANCE Qn0 : THE LEVELOF An BEFORE THE INDICATED STEADYSTATEINPUTCONDITIONS WERE ESTABLISED. Qnn : THE LEVELOF Qn BEFORETHE MOST RECENTACTIVETRANSITIONINDICATEDBY OR a,h : THE LEVELOF THE STEADYSTATEINPUTSA, H, RESPECTIVELY. X : DON’T CARE 2/13 74ACT299 LOGIC DIAGRAM 3/13 74ACT299 TIMING CHART 4/13 74ACT299 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -40 to +85 8 Unit V V V o C ns/V 1) VIN from 0.8 V to 2.0 V 5/13 74ACT299 DC SPECIFICATIONS Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II IOZ ICCT ICC IOLD IOHD Input Leakage Current 3 State Output Leakage Current Max ICC /Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 5.5 VI = V IH or V IL (* ) Test Co nditions Min. VO = 0.1 V or VCC - 0.1 V VO = 0.1 V or VCC - 0.1 V V I (* ) = V IH or V IL IO=-50 µA IO=-50 µA IO=-24 mA IO=-24 mA IO=50 µA IO=50 mA IO=24 mA IO=24 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC -2.1 V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 0.6 4.4 5.4 3.86 4.86 0.001 0.001 2.0 2.0 T yp. 1.5 1.5 1.5 1.5 4.49 5.49 Valu e T A = 25 oC Max. -40 to 85 o C Min. 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.36 0.36 ±0.1 ±0.5 0.1 0.1 0.44 0.44 ±1 ±5 1.5 8 80 75 -75 0.8 0.8 Max. Un it V V V V µA µA mA µA mA mA 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. 6/13 74ACT299 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter V CC (V) tPLH tPHL tPLH tPHL tPHL tPHL tPZL tPZH tPLZ tPHZ tw tw ts th ts th tREM fMAX Propagation Delay Time CLOCK to Q’A, Q’H Propagation Delay Time CLOCK to QA - QH Propagation Delay Time CLEAR to Q’A, Q’ H Propagation Delay Time CLEAR to QA - QH Output Enable Time Output Disable Time CLEAR pulse Width, LOW CLOCK pulse Width Setup Time HIGH or LOW (S0 or S1 to CK) Hold Time HIGH or LOW (S0 or S1 to CK) Setup Time HIGH or LOW (SR or SL to CK) Hold Time HIGH or LOW (SR or SL to CK) Recovery Time CLR to Q Maximum Clock Frequency 5.0(*) 5.0 5.0 5.0 5.0 5.0 (*) T est Con ditio n Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 7.2 10.5 1.0 12.0 7.4 6.0 6.3 7.4 7.2 11.4 10.0 10.5 11.4 9.6 5.0 5.0 6.0 0.0 3.5 2.0 2.0 80 120 80 1.0 1.0 1.0 1.0 1.0 13.0 11.5 12.0 13.0 11.0 5.0 5.0 6.5 0.0 3.5 2.0 2.0 Un it ns ns ns ns ns ns ns ns ns ns ns ns ns MHz (*) (*) (*) (*) 5.0(*) 5.0(*) 5.0(*) 5.0 (*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) *) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter V CC (V) C IN CI/O CPD Input Capacitance Bus Input Capacitance Power Dissipation Capacitance (note 1) 5.0 5.0 5.0 fIN = 10 MHz Test Co nditions Min. T yp. 5 13 160 pF Valu e T A = 25 oC Max. 10 -40 to 85 o C Min. Max. 10 pF Un it 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto 7/13 74ACT299 TEST CIRCUIT T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) SW IT CH Open 2VCC Open WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 8/13 74ACT299 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 9/13 74ACT299 WAVEFORM 4: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 10/13 74ACT299 Plastic DIP-20 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX. DIM. P001J 11/13 74ACT299 SO-20 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 P013L 12/13 74ACT299 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 13/13